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| author | Dmitry Torokhov <dtor@insightbb.com> | 2006-09-19 01:56:44 -0400 |
|---|---|---|
| committer | Dmitry Torokhov <dtor@insightbb.com> | 2006-09-19 01:56:44 -0400 |
| commit | 0612ec48762bf8712db1925b2e67246d2237ebab (patch) | |
| tree | 01b0d69c9c9915015c0f23ad4263646dd5413e99 /include/asm-mips/cpu.h | |
| parent | 4263cf0fac28122c8381b6f4f9441a43cd93c81f (diff) | |
| parent | 47a5c6fa0e204a2b63309c648bb2fde36836c826 (diff) | |
Merge rsync://rsync.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'include/asm-mips/cpu.h')
| -rw-r--r-- | include/asm-mips/cpu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index dff2a0a52f8..d38fdbf845b 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -242,7 +242,7 @@ #define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */ #define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */ #define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */ -#define MIPS_CPU_SUBSET_CACHES 0x00040000 /* P-cache subset enforced */ +#define MIPS_CPU_INCLUSIVE_CACHES 0x00040000 /* P-cache subset enforced */ #define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ #define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ #define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ |