diff options
| author | Dave Jones <davej@redhat.com> | 2007-02-10 20:36:29 -0500 |
|---|---|---|
| committer | Dave Jones <davej@redhat.com> | 2007-02-10 20:36:29 -0500 |
| commit | bd0561c9d8dcbf21cd9aa46c416bbf6a3a12e4b1 (patch) | |
| tree | 64fe15d4db42e0840acea00e4cf7e1855bba9e96 /include/asm-mips/mips-boards/maltaint.h | |
| parent | 348f31ed2bd18391fe5903aa0ad7bfcda6d8ca0b (diff) | |
| parent | 66efc5a7e3061c3597ac43a8bb1026488d57e66b (diff) | |
[CPUFREQ] Fix up merge conflicts with recent ACPI changes.
Signed-off-by: Dave Jones <davej@redhat.com>
Diffstat (limited to 'include/asm-mips/mips-boards/maltaint.h')
| -rw-r--r-- | include/asm-mips/mips-boards/maltaint.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h index da6cc2fbbc7..9180d646611 100644 --- a/include/asm-mips/mips-boards/maltaint.h +++ b/include/asm-mips/mips-boards/maltaint.h @@ -25,6 +25,8 @@ #ifndef _MIPS_MALTAINT_H #define _MIPS_MALTAINT_H +#include <irq.h> + /* * Interrupts 0..15 are used for Malta ISA compatible interrupts */ @@ -33,7 +35,7 @@ /* * Interrupts 16..23 are used for Malta CPU interrupts (nonEIC mode) */ -#define MIPSCPU_INT_BASE 16 +#define MIPSCPU_INT_BASE MIPS_CPU_IRQ_BASE /* CPU interrupt offsets */ #define MIPSCPU_INT_SW0 0 |