MIPS: Move headfiles to new location below arch/mips/include

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

10 files changed, 0 insertions, 1243 deletions

diff --git a/include/asm-mips/mips-boards/bonito64.h b/include/asm-mips/mips-boards/bonito64.h
deleted file mode 100644
index a0f04bb99c9..00000000000
--- a/include/asm-mips/mips-boards/bonito64.h
+++ /dev/null
@@ -1,436 +0,0 @@
-/*
- * Bonito Register Map
- *
- * This file is the original bonito.h from Algorithmics with minor changes
- * to fit into linux.
- *
- * Copyright (c) 1999 Algorithmics Ltd
- *
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2001 MIPS Technologies, Inc.  All rights reserved.
- *
- * Algorithmics gives permission for anyone to use and modify this file
- * without any obligation or license condition except that you retain
- * this copyright message in any source redistribution in whole or part.
- *
- */
-
-/* Revision 1.48 autogenerated on 08/17/99 15:20:01 */
-/* This bonito64 version editted from bonito.h Revision 1.48 on 11/09/00 */
-
-#ifndef _ASM_MIPS_BOARDS_BONITO64_H
-#define _ASM_MIPS_BOARDS_BONITO64_H
-
-#ifdef __ASSEMBLY__
-
-/* offsets from base register */
-#define BONITO(x)	(x)
-
-#elif defined(CONFIG_LEMOTE_FULONG)
-
-#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x)))
-#define BONITO_IRQ_BASE   32
-
-#else
-
-/*
- * Algorithmics Bonito64 system controller register base.
- */
-extern unsigned long _pcictrl_bonito;
-extern unsigned long _pcictrl_bonito_pcicfg;
-
-#define BONITO(x)		*(volatile u32 *)(_pcictrl_bonito + (x))
-
-#endif /* __ASSEMBLY__ */
-
-
-#define BONITO_BOOT_BASE		0x1fc00000
-#define BONITO_BOOT_SIZE		0x00100000
-#define BONITO_BOOT_TOP 		(BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)
-#define BONITO_FLASH_BASE		0x1c000000
-#define BONITO_FLASH_SIZE		0x03000000
-#define BONITO_FLASH_TOP		(BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
-#define BONITO_SOCKET_BASE		0x1f800000
-#define BONITO_SOCKET_SIZE		0x00400000
-#define BONITO_SOCKET_TOP		(BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)
-#define BONITO_REG_BASE 		0x1fe00000
-#define BONITO_REG_SIZE 		0x00040000
-#define BONITO_REG_TOP			(BONITO_REG_BASE+BONITO_REG_SIZE-1)
-#define BONITO_DEV_BASE 		0x1ff00000
-#define BONITO_DEV_SIZE 		0x00100000
-#define BONITO_DEV_TOP			(BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
-#define BONITO_PCILO_BASE		0x10000000
-#define BONITO_PCILO_SIZE		0x0c000000
-#define BONITO_PCILO_TOP		(BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1)
-#define BONITO_PCILO0_BASE		0x10000000
-#define BONITO_PCILO1_BASE		0x14000000
-#define BONITO_PCILO2_BASE		0x18000000
-#define BONITO_PCIHI_BASE		0x20000000
-#define BONITO_PCIHI_SIZE		0x20000000
-#define BONITO_PCIHI_TOP		(BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
-#define BONITO_PCIIO_BASE		0x1fd00000
-#define BONITO_PCIIO_SIZE		0x00100000
-#define BONITO_PCIIO_TOP		(BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1)
-#define BONITO_PCICFG_BASE		0x1fe80000
-#define BONITO_PCICFG_SIZE		0x00080000
-#define BONITO_PCICFG_TOP		(BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1)
-
-
-/* Bonito Register Bases */
-
-#define BONITO_PCICONFIGBASE		0x00
-#define BONITO_REGBASE			0x100
-
-
-/* PCI Configuration  Registers */
-
-#define BONITO_PCI_REG(x)               BONITO(BONITO_PCICONFIGBASE + (x))
-#define BONITO_PCIDID			BONITO_PCI_REG(0x00)
-#define BONITO_PCICMD			BONITO_PCI_REG(0x04)
-#define BONITO_PCICLASS 		BONITO_PCI_REG(0x08)
-#define BONITO_PCILTIMER		BONITO_PCI_REG(0x0c)
-#define BONITO_PCIBASE0 		BONITO_PCI_REG(0x10)
-#define BONITO_PCIBASE1 		BONITO_PCI_REG(0x14)
-#define BONITO_PCIBASE2 		BONITO_PCI_REG(0x18)
-#define BONITO_PCIEXPRBASE		BONITO_PCI_REG(0x30)
-#define BONITO_PCIINT			BONITO_PCI_REG(0x3c)
-
-#define BONITO_PCICMD_PERR_CLR		0x80000000
-#define BONITO_PCICMD_SERR_CLR		0x40000000
-#define BONITO_PCICMD_MABORT_CLR	0x20000000
-#define BONITO_PCICMD_MTABORT_CLR	0x10000000
-#define BONITO_PCICMD_TABORT_CLR	0x08000000
-#define BONITO_PCICMD_MPERR_CLR 	0x01000000
-#define BONITO_PCICMD_PERRRESPEN	0x00000040
-#define BONITO_PCICMD_ASTEPEN		0x00000080
-#define BONITO_PCICMD_SERREN		0x00000100
-#define BONITO_PCILTIMER_BUSLATENCY	0x0000ff00
-#define BONITO_PCILTIMER_BUSLATENCY_SHIFT	8
-
-
-
-
-/* 1. Bonito h/w Configuration */
-/* Power on register */
-
-#define BONITO_BONPONCFG		BONITO(BONITO_REGBASE + 0x00)
-
-#define BONITO_BONPONCFG_SYSCONTROLLERRD	0x00040000
-#define BONITO_BONPONCFG_ROMCS1SAMP	0x00020000
-#define BONITO_BONPONCFG_ROMCS0SAMP	0x00010000
-#define BONITO_BONPONCFG_CPUBIGEND	0x00004000
-/* Added by RPF 11-9-00 */
-#define BONITO_BONPONCFG_BURSTORDER	0x00001000
-/* --- */
-#define BONITO_BONPONCFG_CPUPARITY	0x00002000
-#define BONITO_BONPONCFG_CPUTYPE	0x00000007
-#define BONITO_BONPONCFG_CPUTYPE_SHIFT	0
-#define BONITO_BONPONCFG_PCIRESET_OUT	0x00000008
-#define BONITO_BONPONCFG_IS_ARBITER	0x00000010
-#define BONITO_BONPONCFG_ROMBOOT	0x000000c0
-#define BONITO_BONPONCFG_ROMBOOT_SHIFT	6
-
-#define BONITO_BONPONCFG_ROMBOOT_FLASH	(0x0<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
-#define BONITO_BONPONCFG_ROMBOOT_SOCKET (0x1<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
-#define BONITO_BONPONCFG_ROMBOOT_SDRAM	(0x2<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
-#define BONITO_BONPONCFG_ROMBOOT_CPURESET	(0x3<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
-
-#define BONITO_BONPONCFG_ROMCS0WIDTH	0x00000100
-#define BONITO_BONPONCFG_ROMCS1WIDTH	0x00000200
-#define BONITO_BONPONCFG_ROMCS0FAST	0x00000400
-#define BONITO_BONPONCFG_ROMCS1FAST	0x00000800
-#define BONITO_BONPONCFG_CONFIG_DIS	0x00000020
-
-
-/* Other Bonito configuration */
-
-#define BONITO_BONGENCFG_OFFSET         0x4
-#define BONITO_BONGENCFG		BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET)
-
-#define BONITO_BONGENCFG_DEBUGMODE	0x00000001
-#define BONITO_BONGENCFG_SNOOPEN	0x00000002
-#define BONITO_BONGENCFG_CPUSELFRESET	0x00000004
-
-#define BONITO_BONGENCFG_FORCE_IRQA	0x00000008
-#define BONITO_BONGENCFG_IRQA_ISOUT	0x00000010
-#define BONITO_BONGENCFG_IRQA_FROM_INT1 0x00000020
-#define BONITO_BONGENCFG_BYTESWAP	0x00000040
-
-#define BONITO_BONGENCFG_UNCACHED	0x00000080
-#define BONITO_BONGENCFG_PREFETCHEN	0x00000100
-#define BONITO_BONGENCFG_WBEHINDEN	0x00000200
-#define BONITO_BONGENCFG_CACHEALG	0x00000c00
-#define BONITO_BONGENCFG_CACHEALG_SHIFT 10
-#define BONITO_BONGENCFG_PCIQUEUE	0x00001000
-#define BONITO_BONGENCFG_CACHESTOP	0x00002000
-#define BONITO_BONGENCFG_MSTRBYTESWAP	0x00004000
-#define BONITO_BONGENCFG_BUSERREN	0x00008000
-#define BONITO_BONGENCFG_NORETRYTIMEOUT 0x00010000
-#define BONITO_BONGENCFG_SHORTCOPYTIMEOUT	0x00020000
-
-/* 2. IO & IDE configuration */
-
-#define BONITO_IODEVCFG 		BONITO(BONITO_REGBASE + 0x08)
-
-/* 3. IO & IDE configuration */
-
-#define BONITO_SDCFG			BONITO(BONITO_REGBASE + 0x0c)
-
-/* 4. PCI address map control */
-
-#define BONITO_PCIMAP			BONITO(BONITO_REGBASE + 0x10)
-#define BONITO_PCIMEMBASECFG		BONITO(BONITO_REGBASE + 0x14)
-#define BONITO_PCIMAP_CFG		BONITO(BONITO_REGBASE + 0x18)
-
-/* 5. ICU & GPIO regs */
-
-/* GPIO Regs - r/w */
-
-#define BONITO_GPIODATA_OFFSET          0x1c
-#define BONITO_GPIODATA 		BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET)
-#define BONITO_GPIOIE			BONITO(BONITO_REGBASE + 0x20)
-
-/* ICU Configuration Regs - r/w */
-
-#define BONITO_INTEDGE			BONITO(BONITO_REGBASE + 0x24)
-#define BONITO_INTSTEER 		BONITO(BONITO_REGBASE + 0x28)
-#define BONITO_INTPOL			BONITO(BONITO_REGBASE + 0x2c)
-
-/* ICU Enable Regs - IntEn & IntISR are r/o. */
-
-#define BONITO_INTENSET 		BONITO(BONITO_REGBASE + 0x30)
-#define BONITO_INTENCLR 		BONITO(BONITO_REGBASE + 0x34)
-#define BONITO_INTEN			BONITO(BONITO_REGBASE + 0x38)
-#define BONITO_INTISR			BONITO(BONITO_REGBASE + 0x3c)
-
-/* PCI mail boxes */
-
-#define BONITO_PCIMAIL0_OFFSET          0x40
-#define BONITO_PCIMAIL1_OFFSET          0x44
-#define BONITO_PCIMAIL2_OFFSET          0x48
-#define BONITO_PCIMAIL3_OFFSET          0x4c
-#define BONITO_PCIMAIL0 		BONITO(BONITO_REGBASE + 0x40)
-#define BONITO_PCIMAIL1 		BONITO(BONITO_REGBASE + 0x44)
-#define BONITO_PCIMAIL2 		BONITO(BONITO_REGBASE + 0x48)
-#define BONITO_PCIMAIL3 		BONITO(BONITO_REGBASE + 0x4c)
-
-
-/* 6. PCI cache */
-
-#define BONITO_PCICACHECTRL		BONITO(BONITO_REGBASE + 0x50)
-#define BONITO_PCICACHETAG		BONITO(BONITO_REGBASE + 0x54)
-
-#define BONITO_PCIBADADDR		BONITO(BONITO_REGBASE + 0x58)
-#define BONITO_PCIMSTAT 		BONITO(BONITO_REGBASE + 0x5c)
-
-
-/*
-#define BONITO_PCIRDPOST		BONITO(BONITO_REGBASE + 0x60)
-#define BONITO_PCIDATA			BONITO(BONITO_REGBASE + 0x64)
-*/
-
-/* 7. IDE DMA & Copier */
-
-#define BONITO_CONFIGBASE		0x000
-#define BONITO_BONITOBASE		0x100
-#define BONITO_LDMABASE 		0x200
-#define BONITO_COPBASE			0x300
-#define BONITO_REG_BLOCKMASK		0x300
-
-#define BONITO_LDMACTRL 		BONITO(BONITO_LDMABASE + 0x0)
-#define BONITO_LDMASTAT 		BONITO(BONITO_LDMABASE + 0x0)
-#define BONITO_LDMAADDR 		BONITO(BONITO_LDMABASE + 0x4)
-#define BONITO_LDMAGO			BONITO(BONITO_LDMABASE + 0x8)
-#define BONITO_LDMADATA 		BONITO(BONITO_LDMABASE + 0xc)
-
-#define BONITO_COPCTRL			BONITO(BONITO_COPBASE + 0x0)
-#define BONITO_COPSTAT			BONITO(BONITO_COPBASE + 0x0)
-#define BONITO_COPPADDR 		BONITO(BONITO_COPBASE + 0x4)
-#define BONITO_COPDADDR 		BONITO(BONITO_COPBASE + 0x8)
-#define BONITO_COPGO			BONITO(BONITO_COPBASE + 0xc)
-
-
-/* ###### Bit Definitions for individual Registers #### */
-
-/* Gen DMA. */
-
-#define BONITO_IDECOPDADDR_DMA_DADDR	0x0ffffffc
-#define BONITO_IDECOPDADDR_DMA_DADDR_SHIFT	2
-#define BONITO_IDECOPPADDR_DMA_PADDR	0xfffffffc
-#define BONITO_IDECOPPADDR_DMA_PADDR_SHIFT	2
-#define BONITO_IDECOPGO_DMA_SIZE	0x0000fffe
-#define BONITO_IDECOPGO_DMA_SIZE_SHIFT	0
-#define BONITO_IDECOPGO_DMA_WRITE	0x00010000
-#define BONITO_IDECOPGO_DMAWCOUNT	0x000f0000
-#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT	16
-
-#define BONITO_IDECOPCTRL_DMA_STARTBIT	0x80000000
-#define BONITO_IDECOPCTRL_DMA_RSTBIT	0x40000000
-
-/* DRAM - sdCfg */
-
-#define BONITO_SDCFG_AROWBITS		0x00000003
-#define BONITO_SDCFG_AROWBITS_SHIFT	0
-#define BONITO_SDCFG_ACOLBITS		0x0000000c
-#define BONITO_SDCFG_ACOLBITS_SHIFT	2
-#define BONITO_SDCFG_ABANKBIT		0x00000010
-#define BONITO_SDCFG_ASIDES		0x00000020
-#define BONITO_SDCFG_AABSENT		0x00000040
-#define BONITO_SDCFG_AWIDTH64		0x00000080
-
-#define BONITO_SDCFG_BROWBITS		0x00000300
-#define BONITO_SDCFG_BROWBITS_SHIFT	8
-#define BONITO_SDCFG_BCOLBITS		0x00000c00
-#define BONITO_SDCFG_BCOLBITS_SHIFT	10
-#define BONITO_SDCFG_BBANKBIT		0x00001000
-#define BONITO_SDCFG_BSIDES		0x00002000
-#define BONITO_SDCFG_BABSENT		0x00004000
-#define BONITO_SDCFG_BWIDTH64		0x00008000
-
-#define BONITO_SDCFG_EXTRDDATA		0x00010000
-#define BONITO_SDCFG_EXTRASCAS		0x00020000
-#define BONITO_SDCFG_EXTPRECH		0x00040000
-#define BONITO_SDCFG_EXTRASWIDTH	0x00180000
-#define BONITO_SDCFG_EXTRASWIDTH_SHIFT	19
-/* Changed by RPF 11-9-00 */
-#define BONITO_SDCFG_DRAMMODESET	0x00200000
-/* --- */
-#define BONITO_SDCFG_DRAMEXTREGS	0x00400000
-#define BONITO_SDCFG_DRAMPARITY 	0x00800000
-/* Added by RPF 11-9-00 */
-#define BONITO_SDCFG_DRAMBURSTLEN 	0x03000000
-#define BONITO_SDCFG_DRAMBURSTLEN_SHIFT	24
-#define BONITO_SDCFG_DRAMMODESET_DONE 	0x80000000
-/* --- */
-
-/* PCI Cache - pciCacheCtrl */
-
-#define BONITO_PCICACHECTRL_CACHECMD	0x00000007
-#define BONITO_PCICACHECTRL_CACHECMD_SHIFT	0
-#define BONITO_PCICACHECTRL_CACHECMDLINE	0x00000018
-#define BONITO_PCICACHECTRL_CACHECMDLINE_SHIFT	3
-#define BONITO_PCICACHECTRL_CMDEXEC	0x00000020
-
-#define BONITO_PCICACHECTRL_IOBCCOH_PRES	0x00000100
-#define BONITO_PCICACHECTRL_IOBCCOH_EN	0x00000200
-#define BONITO_PCICACHECTRL_CPUCOH_PRES	0x00000400
-#define BONITO_PCICACHECTRL_CPUCOH_EN	0x00000800
-
-#define BONITO_IODEVCFG_BUFFBIT_CS0	0x00000001
-#define BONITO_IODEVCFG_SPEEDBIT_CS0	0x00000002
-#define BONITO_IODEVCFG_MOREABITS_CS0	0x00000004
-
-#define BONITO_IODEVCFG_BUFFBIT_CS1	0x00000008
-#define BONITO_IODEVCFG_SPEEDBIT_CS1	0x00000010
-#define BONITO_IODEVCFG_MOREABITS_CS1	0x00000020
-
-#define BONITO_IODEVCFG_BUFFBIT_CS2	0x00000040
-#define BONITO_IODEVCFG_SPEEDBIT_CS2	0x00000080
-#define BONITO_IODEVCFG_MOREABITS_CS2	0x00000100
-
-#define BONITO_IODEVCFG_BUFFBIT_CS3	0x00000200
-#define BONITO_IODEVCFG_SPEEDBIT_CS3	0x00000400
-#define BONITO_IODEVCFG_MOREABITS_CS3	0x00000800
-
-#define BONITO_IODEVCFG_BUFFBIT_IDE	0x00001000
-#define BONITO_IODEVCFG_SPEEDBIT_IDE	0x00002000
-#define BONITO_IODEVCFG_WORDSWAPBIT_IDE 0x00004000
-#define BONITO_IODEVCFG_MODEBIT_IDE	0x00008000
-#define BONITO_IODEVCFG_DMAON_IDE	0x001f0000
-#define BONITO_IODEVCFG_DMAON_IDE_SHIFT 16
-#define BONITO_IODEVCFG_DMAOFF_IDE	0x01e00000
-#define BONITO_IODEVCFG_DMAOFF_IDE_SHIFT	21
-#define BONITO_IODEVCFG_EPROMSPLIT	0x02000000
-/* Added by RPF 11-9-00 */
-#define BONITO_IODEVCFG_CPUCLOCKPERIOD	0xfc000000
-#define BONITO_IODEVCFG_CPUCLOCKPERIOD_SHIFT 26
-/* --- */
-
-/* gpio */
-#define BONITO_GPIO_GPIOW		0x000003ff
-#define BONITO_GPIO_GPIOW_SHIFT 	0
-#define BONITO_GPIO_GPIOR		0x01ff0000
-#define BONITO_GPIO_GPIOR_SHIFT 	16
-#define BONITO_GPIO_GPINR		0xfe000000
-#define BONITO_GPIO_GPINR_SHIFT 	25
-#define BONITO_GPIO_IOW(N)		(1<<(BONITO_GPIO_GPIOW_SHIFT+(N)))
-#define BONITO_GPIO_IOR(N)		(1<<(BONITO_GPIO_GPIOR_SHIFT+(N)))
-#define BONITO_GPIO_INR(N)		(1<<(BONITO_GPIO_GPINR_SHIFT+(N)))
-
-/* ICU */
-#define BONITO_ICU_MBOXES		0x0000000f
-#define BONITO_ICU_MBOXES_SHIFT 	0
-#define BONITO_ICU_DMARDY		0x00000010
-#define BONITO_ICU_DMAEMPTY		0x00000020
-#define BONITO_ICU_COPYRDY		0x00000040
-#define BONITO_ICU_COPYEMPTY		0x00000080
-#define BONITO_ICU_COPYERR		0x00000100
-#define BONITO_ICU_PCIIRQ		0x00000200
-#define BONITO_ICU_MASTERERR		0x00000400
-#define BONITO_ICU_SYSTEMERR		0x00000800
-#define BONITO_ICU_DRAMPERR		0x00001000
-#define BONITO_ICU_RETRYERR		0x00002000
-#define BONITO_ICU_GPIOS		0x01ff0000
-#define BONITO_ICU_GPIOS_SHIFT		16
-#define BONITO_ICU_GPINS		0x7e000000
-#define BONITO_ICU_GPINS_SHIFT		25
-#define BONITO_ICU_MBOX(N)		(1<<(BONITO_ICU_MBOXES_SHIFT+(N)))
-#define BONITO_ICU_GPIO(N)		(1<<(BONITO_ICU_GPIOS_SHIFT+(N)))
-#define BONITO_ICU_GPIN(N)		(1<<(BONITO_ICU_GPINS_SHIFT+(N)))
-
-/* pcimap */
-
-#define BONITO_PCIMAP_PCIMAP_LO0	0x0000003f
-#define BONITO_PCIMAP_PCIMAP_LO0_SHIFT	0
-#define BONITO_PCIMAP_PCIMAP_LO1	0x00000fc0
-#define BONITO_PCIMAP_PCIMAP_LO1_SHIFT	6
-#define BONITO_PCIMAP_PCIMAP_LO2	0x0003f000
-#define BONITO_PCIMAP_PCIMAP_LO2_SHIFT	12
-#define BONITO_PCIMAP_PCIMAP_2		0x00040000
-#define BONITO_PCIMAP_WIN(WIN, ADDR)	((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
-
-#define BONITO_PCIMAP_WINSIZE           (1<<26)
-#define BONITO_PCIMAP_WINOFFSET(ADDR)	((ADDR) & (BONITO_PCIMAP_WINSIZE - 1))
-#define BONITO_PCIMAP_WINBASE(ADDR)	((ADDR) << 26)
-
-/* pcimembaseCfg */
-
-#define BONITO_PCIMEMBASECFG_MASK               0xf0000000
-#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK	0x0000001f
-#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT	0
-#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS	0x000003e0
-#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT	5
-#define BONITO_PCIMEMBASECFG_MEMBASE0_CACHED	0x00000400
-#define BONITO_PCIMEMBASECFG_MEMBASE0_IO	0x00000800
-
-#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK	0x0001f000
-#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT	12
-#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS	0x003e0000
-#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT	17
-#define BONITO_PCIMEMBASECFG_MEMBASE1_CACHED	0x00400000
-#define BONITO_PCIMEMBASECFG_MEMBASE1_IO	0x00800000
-
-#define BONITO_PCIMEMBASECFG_ASHIFT	23
-#define BONITO_PCIMEMBASECFG_AMASK              0x007fffff
-#define BONITO_PCIMEMBASECFGSIZE(WIN, SIZE)	(((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)
-#define BONITO_PCIMEMBASECFGBASE(WIN, BASE)	(((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS)
-
-#define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG)  (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK)
-
-
-#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)  ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
-#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)  ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
-#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
-
-#define BONITO_PCITOPHYS(WIN, ADDR, CFG)          ( \
-                                                  (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)))) | \
-                                                  (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG)) \
-                                                )
-
-/* PCICmd */
-
-#define BONITO_PCICMD_MEMEN		0x00000002
-#define BONITO_PCICMD_MSTREN		0x00000004
-
-
-#endif /* _ASM_MIPS_BOARDS_BONITO64_H */
diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h
deleted file mode 100644
index 7f0b034dd9a..00000000000
--- a/include/asm-mips/mips-boards/generic.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * Defines of the MIPS boards specific address-MAP, registers, etc.
- */
-#ifndef __ASM_MIPS_BOARDS_GENERIC_H
-#define __ASM_MIPS_BOARDS_GENERIC_H
-
-#include <asm/addrspace.h>
-#include <asm/byteorder.h>
-#include <asm/mips-boards/bonito64.h>
-
-/*
- * Display register base.
- */
-#define ASCII_DISPLAY_WORD_BASE    0x1f000410
-#define ASCII_DISPLAY_POS_BASE     0x1f000418
-
-
-/*
- * Yamon Prom print address.
- */
-#define YAMON_PROM_PRINT_ADDR      0x1fc00504
-
-
-/*
- * Reset register.
- */
-#define SOFTRES_REG       0x1f000500
-#define GORESET           0x42
-
-/*
- * Revision register.
- */
-#define MIPS_REVISION_REG                  0x1fc00010
-#define MIPS_REVISION_CORID_QED_RM5261     0
-#define MIPS_REVISION_CORID_CORE_LV        1
-#define MIPS_REVISION_CORID_BONITO64       2
-#define MIPS_REVISION_CORID_CORE_20K       3
-#define MIPS_REVISION_CORID_CORE_FPGA      4
-#define MIPS_REVISION_CORID_CORE_MSC       5
-#define MIPS_REVISION_CORID_CORE_EMUL      6
-#define MIPS_REVISION_CORID_CORE_FPGA2     7
-#define MIPS_REVISION_CORID_CORE_FPGAR2    8
-#define MIPS_REVISION_CORID_CORE_FPGA3     9
-#define MIPS_REVISION_CORID_CORE_24K       10
-#define MIPS_REVISION_CORID_CORE_FPGA4     11
-#define MIPS_REVISION_CORID_CORE_FPGA5     12
-
-/**** Artificial corid defines ****/
-/*
- *  CoreEMUL with   Bonito   System Controller is treated like a Core20K
- *  CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC
- */
-#define MIPS_REVISION_CORID_CORE_EMUL_BON  -1
-#define MIPS_REVISION_CORID_CORE_EMUL_MSC  -2
-
-#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
-
-extern int mips_revision_corid;
-
-#define MIPS_REVISION_SCON_OTHER	   0
-#define MIPS_REVISION_SCON_SOCITSC	   1
-#define MIPS_REVISION_SCON_SOCITSCP	   2
-
-/* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */
-#define MIPS_REVISION_SCON_UNKNOWN	   -1
-#define MIPS_REVISION_SCON_GT64120	   -2
-#define MIPS_REVISION_SCON_BONITO	   -3
-#define MIPS_REVISION_SCON_BRTL		   -4
-#define MIPS_REVISION_SCON_SOCIT	   -5
-#define MIPS_REVISION_SCON_ROCIT	   -6
-
-#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff)
-
-extern int mips_revision_sconid;
-
-extern void mips_reboot_setup(void);
-
-#ifdef CONFIG_PCI
-extern void mips_pcibios_init(void);
-#else
-#define mips_pcibios_init() do { } while (0)
-#endif
-
-#ifdef CONFIG_KGDB
-extern void kgdb_config(void);
-#endif
-
-#endif  /* __ASM_MIPS_BOARDS_GENERIC_H */
diff --git a/include/asm-mips/mips-boards/launch.h b/include/asm-mips/mips-boards/launch.h
deleted file mode 100644
index d8ae7f95a52..00000000000
--- a/include/asm-mips/mips-boards/launch.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- *
- */
-
-#ifndef _ASSEMBLER_
-
-struct cpulaunch {
-    unsigned long	pc;
-    unsigned long	gp;
-    unsigned long	sp;
-    unsigned long	a0;
-    unsigned long	_pad[3]; /* pad to cache line size to avoid thrashing */
-    unsigned long	flags;
-};
-
-#else
-
-#define LOG2CPULAUNCH	5
-#define	LAUNCH_PC	0
-#define	LAUNCH_GP	4
-#define	LAUNCH_SP	8
-#define	LAUNCH_A0	12
-#define	LAUNCH_FLAGS	28
-
-#endif
-
-#define LAUNCH_FREADY	1
-#define LAUNCH_FGO	2
-#define LAUNCH_FGONE	4
-
-#define CPULAUNCH	0x00000f00
-#define NCPULAUNCH	8
-
-/* Polling period in count cycles for secondary CPU's */
-#define LAUNCHPERIOD	10000
diff --git a/include/asm-mips/mips-boards/malta.h b/include/asm-mips/mips-boards/malta.h
deleted file mode 100644
index c1891578fa6..00000000000
--- a/include/asm-mips/mips-boards/malta.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * Defines of the Malta board specific address-MAP, registers, etc.
- */
-#ifndef __ASM_MIPS_BOARDS_MALTA_H
-#define __ASM_MIPS_BOARDS_MALTA_H
-
-#include <asm/addrspace.h>
-#include <asm/io.h>
-#include <asm/mips-boards/msc01_pci.h>
-#include <asm/gt64120.h>
-
-/* Mips interrupt controller found in SOCit variations */
-#define MIPS_MSC01_IC_REG_BASE		0x1bc40000
-#define MIPS_SOCITSC_IC_REG_BASE	0x1ffa0000
-
-/*
- * Malta I/O ports base address for the Galileo GT64120 and Algorithmics
- * Bonito system controllers.
- */
-#define MALTA_GT_PORT_BASE      get_gt_port_base(GT_PCI0IOLD_OFS)
-#define MALTA_BONITO_PORT_BASE  ((unsigned long)ioremap (0x1fd00000, 0x10000))
-#define MALTA_MSC_PORT_BASE     get_msc_port_base(MSC01_PCI_SC2PIOBASL)
-
-static inline unsigned long get_gt_port_base(unsigned long reg)
-{
-	unsigned long addr;
-	addr = GT_READ(reg);
-	return (unsigned long) ioremap (((addr & 0xffff) << 21), 0x10000);
-}
-
-static inline unsigned long get_msc_port_base(unsigned long reg)
-{
-	unsigned long addr;
-	MSC_READ(reg, addr);
-	return (unsigned long) ioremap(addr, 0x10000);
-}
-
-/*
- * GCMP Specific definitions
- */
-#define GCMP_BASE_ADDR			0x1fbf8000
-#define GCMP_ADDRSPACE_SZ		(256 * 1024)
-
-/*
- * GIC Specific definitions
- */
-#define GIC_BASE_ADDR			0x1bdc0000
-#define GIC_ADDRSPACE_SZ		(128 * 1024)
-
-/*
- * MSC01 BIU Specific definitions
- * FIXME : These should be elsewhere ?
- */
-#define MSC01_BIU_REG_BASE		0x1bc80000
-#define MSC01_BIU_ADDRSPACE_SZ		(256 * 1024)
-#define MSC01_SC_CFG_OFS		0x0110
-#define MSC01_SC_CFG_GICPRES_MSK	0x00000004
-#define MSC01_SC_CFG_GICPRES_SHF	2
-#define MSC01_SC_CFG_GICENA_SHF		3
-
-/*
- * Malta RTC-device indirect register access.
- */
-#define MALTA_RTC_ADR_REG       0x70
-#define MALTA_RTC_DAT_REG       0x71
-
-/*
- * Malta SMSC FDC37M817 Super I/O Controller register.
- */
-#define SMSC_CONFIG_REG		0x3f0
-#define SMSC_DATA_REG		0x3f1
-
-#define SMSC_CONFIG_DEVNUM	0x7
-#define SMSC_CONFIG_ACTIVATE	0x30
-#define SMSC_CONFIG_ENTER	0x55
-#define SMSC_CONFIG_EXIT	0xaa
-
-#define SMSC_CONFIG_DEVNUM_FLOPPY     0
-
-#define SMSC_CONFIG_ACTIVATE_ENABLE   1
-
-#define SMSC_WRITE(x, a)     outb(x, a)
-
-#define MALTA_JMPRS_REG		0x1f000210
-
-#endif /* __ASM_MIPS_BOARDS_MALTA_H */
diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h
deleted file mode 100644
index cea872fc6f5..00000000000
--- a/include/asm-mips/mips-boards/maltaint.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- * Defines for the Malta interrupt controller.
- *
- */
-#ifndef _MIPS_MALTAINT_H
-#define _MIPS_MALTAINT_H
-
-#include <irq.h>
-
-/*
- * Interrupts 0..15 are used for Malta ISA compatible interrupts
- */
-#define MALTA_INT_BASE		0
-
-/* CPU interrupt offsets */
-#define MIPSCPU_INT_SW0		0
-#define MIPSCPU_INT_SW1		1
-#define MIPSCPU_INT_MB0		2
-#define MIPSCPU_INT_I8259A	MIPSCPU_INT_MB0
-#define MIPSCPU_INT_MB1		3
-#define MIPSCPU_INT_SMI		MIPSCPU_INT_MB1
-#define MIPSCPU_INT_IPI0	MIPSCPU_INT_MB1	/* GIC IPI */
-#define MIPSCPU_INT_MB2		4
-#define MIPSCPU_INT_IPI1	MIPSCPU_INT_MB2	/* GIC IPI */
-#define MIPSCPU_INT_MB3		5
-#define MIPSCPU_INT_COREHI	MIPSCPU_INT_MB3
-#define MIPSCPU_INT_MB4		6
-#define MIPSCPU_INT_CORELO	MIPSCPU_INT_MB4
-
-/*
- * Interrupts 64..127 are used for Soc-it Classic interrupts
- */
-#define MSC01C_INT_BASE		64
-
-/* SOC-it Classic interrupt offsets */
-#define MSC01C_INT_TMR		0
-#define MSC01C_INT_PCI		1
-
-/*
- * Interrupts 64..127 are used for Soc-it EIC interrupts
- */
-#define MSC01E_INT_BASE		64
-
-/* SOC-it EIC interrupt offsets */
-#define MSC01E_INT_SW0		1
-#define MSC01E_INT_SW1		2
-#define MSC01E_INT_MB0		3
-#define MSC01E_INT_I8259A	MSC01E_INT_MB0
-#define MSC01E_INT_MB1		4
-#define MSC01E_INT_SMI		MSC01E_INT_MB1
-#define MSC01E_INT_MB2		5
-#define MSC01E_INT_MB3		6
-#define MSC01E_INT_COREHI	MSC01E_INT_MB3
-#define MSC01E_INT_MB4		7
-#define MSC01E_INT_CORELO	MSC01E_INT_MB4
-#define MSC01E_INT_TMR		8
-#define MSC01E_INT_PCI		9
-#define MSC01E_INT_PERFCTR	10
-#define MSC01E_INT_CPUCTR	11
-
-/* GIC's Nomenclature for Core Interrupt Pins on the Malta */
-#define GIC_CPU_INT0		0 /* Core Interrupt 2 	*/
-#define GIC_CPU_INT1		1 /* .			*/
-#define GIC_CPU_INT2		2 /* .			*/
-#define GIC_CPU_INT3		3 /* .			*/
-#define GIC_CPU_INT4		4 /* .			*/
-#define GIC_CPU_INT5		5 /* Core Interrupt 5   */
-
-#define GIC_EXT_INTR(x)		x
-
-/* Dummy data */
-#define X			0xdead
-
-/* External Interrupts used for IPI */
-#define GIC_IPI_EXT_INTR_RESCHED_VPE0	16
-#define GIC_IPI_EXT_INTR_CALLFNC_VPE0	17
-#define GIC_IPI_EXT_INTR_RESCHED_VPE1	18
-#define GIC_IPI_EXT_INTR_CALLFNC_VPE1	19
-#define GIC_IPI_EXT_INTR_RESCHED_VPE2	20
-#define GIC_IPI_EXT_INTR_CALLFNC_VPE2	21
-#define GIC_IPI_EXT_INTR_RESCHED_VPE3	22
-#define GIC_IPI_EXT_INTR_CALLFNC_VPE3	23
-
-#define MIPS_GIC_IRQ_BASE	(MIPS_CPU_IRQ_BASE + 8)
-
-#ifndef __ASSEMBLY__
-extern void maltaint_init(void);
-#endif
-
-#endif /* !(_MIPS_MALTAINT_H) */
diff --git a/include/asm-mips/mips-boards/msc01_pci.h b/include/asm-mips/mips-boards/msc01_pci.h
deleted file mode 100644
index e036b7dd6de..00000000000
--- a/include/asm-mips/mips-boards/msc01_pci.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * PCI Register definitions for the MIPS System Controller.
- *
- * Copyright (C) 2002, 2005  MIPS Technologies, Inc.  All rights reserved.
- *	Authors: Carsten Langgaard <carstenl@mips.com>
- *		 Maciej W. Rozycki <macro@mips.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_MIPS_BOARDS_MSC01_PCI_H
-#define __ASM_MIPS_BOARDS_MSC01_PCI_H
-
-/*
- * Register offset addresses
- */
-
-#define MSC01_PCI_ID_OFS		0x0000
-#define MSC01_PCI_SC2PMBASL_OFS		0x0208
-#define MSC01_PCI_SC2PMMSKL_OFS		0x0218
-#define MSC01_PCI_SC2PMMAPL_OFS		0x0228
-#define MSC01_PCI_SC2PIOBASL_OFS	0x0248
-#define MSC01_PCI_SC2PIOMSKL_OFS	0x0258
-#define MSC01_PCI_SC2PIOMAPL_OFS	0x0268
-#define MSC01_PCI_P2SCMSKL_OFS		0x0308
-#define MSC01_PCI_P2SCMAPL_OFS		0x0318
-#define MSC01_PCI_INTCFG_OFS		0x0600
-#define MSC01_PCI_INTSTAT_OFS		0x0608
-#define MSC01_PCI_CFGADDR_OFS		0x0610
-#define MSC01_PCI_CFGDATA_OFS		0x0618
-#define MSC01_PCI_IACK_OFS		0x0620
-#define MSC01_PCI_HEAD0_OFS		0x2000	/* DevID, VendorID */
-#define MSC01_PCI_HEAD1_OFS		0x2008	/* Status, Command */
-#define MSC01_PCI_HEAD2_OFS		0x2010	/* Class code, RevID */
-#define MSC01_PCI_HEAD3_OFS		0x2018	/* bist, header, latency */
-#define MSC01_PCI_HEAD4_OFS		0x2020	/* BAR 0 */
-#define MSC01_PCI_HEAD5_OFS		0x2028	/* BAR 1 */
-#define MSC01_PCI_HEAD6_OFS		0x2030	/* BAR 2 */
-#define MSC01_PCI_HEAD7_OFS		0x2038	/* BAR 3 */
-#define MSC01_PCI_HEAD8_OFS		0x2040	/* BAR 4 */
-#define MSC01_PCI_HEAD9_OFS		0x2048	/* BAR 5 */
-#define MSC01_PCI_HEAD10_OFS		0x2050	/* CardBus CIS Ptr */
-#define MSC01_PCI_HEAD11_OFS		0x2058	/* SubSystem ID, -VendorID */
-#define MSC01_PCI_HEAD12_OFS		0x2060	/* ROM BAR */
-#define MSC01_PCI_HEAD13_OFS		0x2068	/* Capabilities ptr */
-#define MSC01_PCI_HEAD14_OFS		0x2070	/* reserved */
-#define MSC01_PCI_HEAD15_OFS		0x2078	/* Maxl, ming, intpin, int */
-#define MSC01_PCI_BAR0_OFS		0x2220
-#define MSC01_PCI_CFG_OFS		0x2380
-#define MSC01_PCI_SWAP_OFS		0x2388
-
-
-/*****************************************************************************
- * Register encodings
- ****************************************************************************/
-
-#define MSC01_PCI_ID_ID_SHF		16
-#define MSC01_PCI_ID_ID_MSK		0x00ff0000
-#define MSC01_PCI_ID_ID_HOSTBRIDGE	82
-#define MSC01_PCI_ID_MAR_SHF		8
-#define MSC01_PCI_ID_MAR_MSK		0x0000ff00
-#define MSC01_PCI_ID_MIR_SHF		0
-#define MSC01_PCI_ID_MIR_MSK		0x000000ff
-
-#define MSC01_PCI_SC2PMBASL_BAS_SHF	24
-#define MSC01_PCI_SC2PMBASL_BAS_MSK	0xff000000
-
-#define MSC01_PCI_SC2PMMSKL_MSK_SHF	24
-#define MSC01_PCI_SC2PMMSKL_MSK_MSK	0xff000000
-
-#define MSC01_PCI_SC2PMMAPL_MAP_SHF	24
-#define MSC01_PCI_SC2PMMAPL_MAP_MSK	0xff000000
-
-#define MSC01_PCI_SC2PIOBASL_BAS_SHF	24
-#define MSC01_PCI_SC2PIOBASL_BAS_MSK	0xff000000
-
-#define MSC01_PCI_SC2PIOMSKL_MSK_SHF	24
-#define MSC01_PCI_SC2PIOMSKL_MSK_MSK	0xff000000
-
-#define MSC01_PCI_SC2PIOMAPL_MAP_SHF	24
-#define MSC01_PCI_SC2PIOMAPL_MAP_MSK	0xff000000
-
-#define MSC01_PCI_P2SCMSKL_MSK_SHF	24
-#define MSC01_PCI_P2SCMSKL_MSK_MSK	0xff000000
-
-#define MSC01_PCI_P2SCMAPL_MAP_SHF	24
-#define MSC01_PCI_P2SCMAPL_MAP_MSK	0xff000000
-
-#define MSC01_PCI_INTCFG_RST_SHF	10
-#define MSC01_PCI_INTCFG_RST_MSK	0x00000400
-#define MSC01_PCI_INTCFG_RST_BIT	0x00000400
-#define MSC01_PCI_INTCFG_MWE_SHF	9
-#define MSC01_PCI_INTCFG_MWE_MSK	0x00000200
-#define MSC01_PCI_INTCFG_MWE_BIT	0x00000200
-#define MSC01_PCI_INTCFG_DTO_SHF	8
-#define MSC01_PCI_INTCFG_DTO_MSK	0x00000100
-#define MSC01_PCI_INTCFG_DTO_BIT	0x00000100
-#define MSC01_PCI_INTCFG_MA_SHF		7
-#define MSC01_PCI_INTCFG_MA_MSK		0x00000080
-#define MSC01_PCI_INTCFG_MA_BIT		0x00000080
-#define MSC01_PCI_INTCFG_TA_SHF		6
-#define MSC01_PCI_INTCFG_TA_MSK		0x00000040
-#define MSC01_PCI_INTCFG_TA_BIT		0x00000040
-#define MSC01_PCI_INTCFG_RTY_SHF	5
-#define MSC01_PCI_INTCFG_RTY_MSK	0x00000020
-#define MSC01_PCI_INTCFG_RTY_BIT	0x00000020
-#define MSC01_PCI_INTCFG_MWP_SHF	4
-#define MSC01_PCI_INTCFG_MWP_MSK	0x00000010
-#define MSC01_PCI_INTCFG_MWP_BIT	0x00000010
-#define MSC01_PCI_INTCFG_MRP_SHF	3
-#define MSC01_PCI_INTCFG_MRP_MSK	0x00000008
-#define MSC01_PCI_INTCFG_MRP_BIT	0x00000008
-#define MSC01_PCI_INTCFG_SWP_SHF	2
-#define MSC01_PCI_INTCFG_SWP_MSK	0x00000004
-#define MSC01_PCI_INTCFG_SWP_BIT	0x00000004
-#define MSC01_PCI_INTCFG_SRP_SHF	1
-#define MSC01_PCI_INTCFG_SRP_MSK	0x00000002
-#define MSC01_PCI_INTCFG_SRP_BIT	0x00000002
-#define MSC01_PCI_INTCFG_SE_SHF		0
-#define MSC01_PCI_INTCFG_SE_MSK		0x00000001
-#define MSC01_PCI_INTCFG_SE_BIT		0x00000001
-
-#define MSC01_PCI_INTSTAT_RST_SHF	10
-#define MSC01_PCI_INTSTAT_RST_MSK	0x00000400
-#define MSC01_PCI_INTSTAT_RST_BIT	0x00000400
-#define MSC01_PCI_INTSTAT_MWE_SHF	9
-#define MSC01_PCI_INTSTAT_MWE_MSK	0x00000200
-#define MSC01_PCI_INTSTAT_MWE_BIT	0x00000200
-#define MSC01_PCI_INTSTAT_DTO_SHF	8
-#define MSC01_PCI_INTSTAT_DTO_MSK	0x00000100
-#define MSC01_PCI_INTSTAT_DTO_BIT	0x00000100
-#define MSC01_PCI_INTSTAT_MA_SHF	7
-#define MSC01_PCI_INTSTAT_MA_MSK	0x00000080
-#define MSC01_PCI_INTSTAT_MA_BIT	0x00000080
-#define MSC01_PCI_INTSTAT_TA_SHF	6
-#define MSC01_PCI_INTSTAT_TA_MSK	0x00000040
-#define MSC01_PCI_INTSTAT_TA_BIT	0x00000040
-#define MSC01_PCI_INTSTAT_RTY_SHF	5
-#define MSC01_PCI_INTSTAT_RTY_MSK	0x00000020
-#define MSC01_PCI_INTSTAT_RTY_BIT	0x00000020
-#define MSC01_PCI_INTSTAT_MWP_SHF	4
-#define MSC01_PCI_INTSTAT_MWP_MSK	0x00000010
-#define MSC01_PCI_INTSTAT_MWP_BIT	0x00000010
-#define MSC01_PCI_INTSTAT_MRP_SHF	3
-#define MSC01_PCI_INTSTAT_MRP_MSK	0x00000008
-#define MSC01_PCI_INTSTAT_MRP_BIT	0x00000008
-#define MSC01_PCI_INTSTAT_SWP_SHF	2
-#define MSC01_PCI_INTSTAT_SWP_MSK	0x00000004
-#define MSC01_PCI_INTSTAT_SWP_BIT	0x00000004
-#define MSC01_PCI_INTSTAT_SRP_SHF	1
-#define MSC01_PCI_INTSTAT_SRP_MSK	0x00000002
-#define MSC01_PCI_INTSTAT_SRP_BIT	0x00000002
-#define MSC01_PCI_INTSTAT_SE_SHF	0
-#define MSC01_PCI_INTSTAT_SE_MSK	0x00000001
-#define MSC01_PCI_INTSTAT_SE_BIT	0x00000001
-
-#define MSC01_PCI_CFGADDR_BNUM_SHF	16
-#define MSC01_PCI_CFGADDR_BNUM_MSK	0x00ff0000
-#define MSC01_PCI_CFGADDR_DNUM_SHF	11
-#define MSC01_PCI_CFGADDR_DNUM_MSK	0x0000f800
-#define MSC01_PCI_CFGADDR_FNUM_SHF	8
-#define MSC01_PCI_CFGADDR_FNUM_MSK	0x00000700
-#define MSC01_PCI_CFGADDR_RNUM_SHF	2
-#define MSC01_PCI_CFGADDR_RNUM_MSK	0x000000fc
-
-#define MSC01_PCI_CFGDATA_DATA_SHF	0
-#define MSC01_PCI_CFGDATA_DATA_MSK	0xffffffff
-
-/* The defines below are ONLY valid for a MEM bar! */
-#define MSC01_PCI_BAR0_SIZE_SHF		4
-#define MSC01_PCI_BAR0_SIZE_MSK		0xfffffff0
-#define MSC01_PCI_BAR0_P_SHF		3
-#define MSC01_PCI_BAR0_P_MSK		0x00000008
-#define MSC01_PCI_BAR0_P_BIT		MSC01_PCI_BAR0_P_MSK
-#define MSC01_PCI_BAR0_D_SHF		1
-#define MSC01_PCI_BAR0_D_MSK		0x00000006
-#define MSC01_PCI_BAR0_T_SHF		0
-#define MSC01_PCI_BAR0_T_MSK		0x00000001
-#define MSC01_PCI_BAR0_T_BIT		MSC01_PCI_BAR0_T_MSK
-
-
-#define MSC01_PCI_CFG_RA_SHF		17
-#define MSC01_PCI_CFG_RA_MSK		0x00020000
-#define MSC01_PCI_CFG_RA_BIT		MSC01_PCI_CFG_RA_MSK
-#define MSC01_PCI_CFG_G_SHF		16
-#define MSC01_PCI_CFG_G_MSK		0x00010000
-#define MSC01_PCI_CFG_G_BIT		MSC01_PCI_CFG_G_MSK
-#define MSC01_PCI_CFG_EN_SHF		15
-#define MSC01_PCI_CFG_EN_MSK		0x00008000
-#define MSC01_PCI_CFG_EN_BIT		MSC01_PCI_CFG_EN_MSK
-#define MSC01_PCI_CFG_MAXRTRY_SHF	0
-#define MSC01_PCI_CFG_MAXRTRY_MSK	0x00000fff
-
-#define MSC01_PCI_SWAP_IO_SHF		18
-#define MSC01_PCI_SWAP_IO_MSK		0x000c0000
-#define MSC01_PCI_SWAP_MEM_SHF		16
-#define MSC01_PCI_SWAP_MEM_MSK		0x00030000
-#define MSC01_PCI_SWAP_BAR0_SHF		0
-#define MSC01_PCI_SWAP_BAR0_MSK		0x00000003
-#define MSC01_PCI_SWAP_NOSWAP		0
-#define MSC01_PCI_SWAP_BYTESWAP		1
-
-/*
- * MIPS System controller PCI register base.
- *
- * FIXME - are these macros specific to Malta and co or to the MSC?  If the
- * latter, they should be moved elsewhere.
- */
-#define MIPS_MSC01_PCI_REG_BASE		0x1bd00000
-#define MIPS_SOCITSC_PCI_REG_BASE	0x1ff10000
-
-extern unsigned long _pcictrl_msc;
-
-#define MSC01_PCI_REG_BASE	_pcictrl_msc
-
-#define MSC_WRITE(reg, data)	do { *(volatile u32 *)(reg) = data; } while (0)
-#define MSC_READ(reg, data)	do { data = *(volatile u32 *)(reg); } while (0)
-
-/*
- * Registers absolute addresses
- */
-
-#define MSC01_PCI_ID		(MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS)
-#define MSC01_PCI_SC2PMBASL	(MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS)
-#define MSC01_PCI_SC2PMMSKL	(MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS)
-#define MSC01_PCI_SC2PMMAPL	(MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS)
-#define MSC01_PCI_SC2PIOBASL	(MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS)
-#define MSC01_PCI_SC2PIOMSKL	(MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS)
-#define MSC01_PCI_SC2PIOMAPL	(MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS)
-#define MSC01_PCI_P2SCMSKL	(MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS)
-#define MSC01_PCI_P2SCMAPL	(MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS)
-#define MSC01_PCI_INTCFG	(MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS)
-#define MSC01_PCI_INTSTAT	(MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS)
-#define MSC01_PCI_CFGADDR	(MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS)
-#define MSC01_PCI_CFGDATA	(MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS)
-#define MSC01_PCI_IACK		(MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS)
-#define MSC01_PCI_HEAD0		(MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS)
-#define MSC01_PCI_HEAD1		(MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS)
-#define MSC01_PCI_HEAD2		(MSC01_PCI_REG_BASE + MSC01_PCI_HEAD2_OFS)
-#define MSC01_PCI_HEAD3		(MSC01_PCI_REG_BASE + MSC01_PCI_HEAD3_OFS)
-#define MSC01_PCI_HEAD4		(MSC01_PCI_REG_BASE + MSC01_PCI_HEAD4_OFS)
-#define MSC01_PCI_HEAD5		(MSC01_PCI_REG_BASE + MSC01_PCI_HEAD5_OFS)
-#define MSC01_PCI_HEAD6		(MSC01_PCI_REG_BASE + MSC01_PCI_HEAD6_OFS)
-#define MSC01_PCI_HEAD7		(MSC01_PCI_REG_BASE + MSC01_PCI_HEAD7_OFS)
-#define MSC01_PCI_HEAD8		(MSC01_PCI_REG_BASE + MSC01_PCI_HEAD8_OFS)
-#define MSC01_PCI_HEAD9		(MSC01_PCI_REG_BASE + MSC01_PCI_HEAD9_OFS)
-#define MSC01_PCI_HEAD10	(MSC01_PCI_REG_BASE + MSC01_PCI_HEAD10_OFS)
-#define MSC01_PCI_HEAD11	(MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
-#define MSC01_PCI_HEAD12	(MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
-#define MSC01_PCI_HEAD13	(MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
-#define MSC01_PCI_HEAD14	(MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
-#define MSC01_PCI_HEAD15	(MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
-#define MSC01_PCI_BAR0		(MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS)
-#define MSC01_PCI_CFG		(MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS)
-#define MSC01_PCI_SWAP		(MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS)
-
-#endif /* __ASM_MIPS_BOARDS_MSC01_PCI_H */
diff --git a/include/asm-mips/mips-boards/piix4.h b/include/asm-mips/mips-boards/piix4.h
deleted file mode 100644
index 2971d60f2e9..00000000000
--- a/include/asm-mips/mips-boards/piix4.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * Register definitions for Intel PIIX4 South Bridge Device.
- */
-#ifndef __ASM_MIPS_BOARDS_PIIX4_H
-#define __ASM_MIPS_BOARDS_PIIX4_H
-
-/************************************************************************
- *  IO register offsets
- ************************************************************************/
-#define PIIX4_ICTLR1_ICW1	0x20
-#define PIIX4_ICTLR1_ICW2	0x21
-#define PIIX4_ICTLR1_ICW3	0x21
-#define PIIX4_ICTLR1_ICW4	0x21
-#define PIIX4_ICTLR2_ICW1	0xa0
-#define PIIX4_ICTLR2_ICW2	0xa1
-#define PIIX4_ICTLR2_ICW3	0xa1
-#define PIIX4_ICTLR2_ICW4	0xa1
-#define PIIX4_ICTLR1_OCW1	0x21
-#define PIIX4_ICTLR1_OCW2	0x20
-#define PIIX4_ICTLR1_OCW3	0x20
-#define PIIX4_ICTLR1_OCW4	0x20
-#define PIIX4_ICTLR2_OCW1	0xa1
-#define PIIX4_ICTLR2_OCW2	0xa0
-#define PIIX4_ICTLR2_OCW3	0xa0
-#define PIIX4_ICTLR2_OCW4	0xa0
-
-
-/************************************************************************
- *  Register encodings.
- ************************************************************************/
-#define PIIX4_OCW2_NSEOI	(0x1 << 5)
-#define PIIX4_OCW2_SEOI		(0x3 << 5)
-#define PIIX4_OCW2_RNSEOI	(0x5 << 5)
-#define PIIX4_OCW2_RAEOIS	(0x4 << 5)
-#define PIIX4_OCW2_RAEOIC	(0x0 << 5)
-#define PIIX4_OCW2_RSEOI	(0x7 << 5)
-#define PIIX4_OCW2_SP		(0x6 << 5)
-#define PIIX4_OCW2_NOP		(0x2 << 5)
-
-#define PIIX4_OCW2_SEL          (0x0 << 3)
-
-#define PIIX4_OCW2_ILS_0	0
-#define PIIX4_OCW2_ILS_1	1
-#define PIIX4_OCW2_ILS_2	2
-#define PIIX4_OCW2_ILS_3	3
-#define PIIX4_OCW2_ILS_4	4
-#define PIIX4_OCW2_ILS_5	5
-#define PIIX4_OCW2_ILS_6	6
-#define PIIX4_OCW2_ILS_7	7
-#define PIIX4_OCW2_ILS_8	0
-#define PIIX4_OCW2_ILS_9	1
-#define PIIX4_OCW2_ILS_10	2
-#define PIIX4_OCW2_ILS_11	3
-#define PIIX4_OCW2_ILS_12	4
-#define PIIX4_OCW2_ILS_13	5
-#define PIIX4_OCW2_ILS_14	6
-#define PIIX4_OCW2_ILS_15	7
-
-#define PIIX4_OCW3_SEL          (0x1 << 3)
-
-#define PIIX4_OCW3_IRR          0x2
-#define PIIX4_OCW3_ISR          0x3
-
-#endif /* __ASM_MIPS_BOARDS_PIIX4_H */
diff --git a/include/asm-mips/mips-boards/prom.h b/include/asm-mips/mips-boards/prom.h
deleted file mode 100644
index a9db576a976..00000000000
--- a/include/asm-mips/mips-boards/prom.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- * MIPS boards bootprom interface for the Linux kernel.
- *
- */
-
-#ifndef _MIPS_PROM_H
-#define _MIPS_PROM_H
-
-extern char *prom_getcmdline(void);
-extern char *prom_getenv(char *name);
-extern void prom_init_cmdline(void);
-extern void prom_meminit(void);
-extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
-extern void mips_display_message(const char *str);
-extern void mips_display_word(unsigned int num);
-extern void mips_scroll_message(void);
-extern int get_ethernet_addr(char *ethernet_addr);
-
-/* Memory descriptor management. */
-#define PROM_MAX_PMEMBLOCKS    32
-struct prom_pmemblock {
-        unsigned long base; /* Within KSEG0. */
-        unsigned int size;  /* In bytes. */
-        unsigned int type;  /* free or prom memory */
-};
-
-#endif /* !(_MIPS_PROM_H) */
diff --git a/include/asm-mips/mips-boards/sim.h b/include/asm-mips/mips-boards/sim.h
deleted file mode 100644
index acb7c2331d9..00000000000
--- a/include/asm-mips/mips-boards/sim.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- */
-
-#ifndef _ASM_MIPS_BOARDS_SIM_H
-#define _ASM_MIPS_BOARDS_SIM_H
-
-#define STATS_ON        1
-#define STATS_OFF       2
-#define STATS_CLEAR     3
-#define STATS_DUMP      4
-#define TRACE_ON		5
-#define TRACE_OFF       6
-
-
-#define simcfg(code)						\
-({					   \
-	__asm__  __volatile__( \
-        "sltiu $0,$0, %0" \
-		::"i"(code)					\
-		); \
-})
-
-
-
-#endif
diff --git a/include/asm-mips/mips-boards/simint.h b/include/asm-mips/mips-boards/simint.h
deleted file mode 100644
index 8ef6db76d5c..00000000000
--- a/include/asm-mips/mips-boards/simint.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- */
-#ifndef _MIPS_SIMINT_H
-#define _MIPS_SIMINT_H
-
-#include <irq.h>
-
-#define SIM_INT_BASE		0
-#define MIPSCPU_INT_MB0		2
-#define MIPS_CPU_TIMER_IRQ	7
-
-
-#define MSC01E_INT_BASE		64
-
-#define MSC01E_INT_CPUCTR	11
-
-#endif