diff options
| author | Chris Dearman <chris@mips.com> | 2007-09-19 00:46:32 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2008-04-28 17:14:25 +0100 |
| commit | 962f480e0f9024ecdcfe2ba1d216c038ee328ced (patch) | |
| tree | 7bdc4f14bd9e894ed3178b3a9b6ec235710868a6 /include/asm-mips/pgtable-bits.h | |
| parent | 0bfa130e741f8f73a7bbf6a89aad4816e9094a71 (diff) | |
[MIPS] All MIPS32 processors support64-bit physical addresses.
Still, only the 4K may actually implement it.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/pgtable-bits.h')
| -rw-r--r-- | include/asm-mips/pgtable-bits.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h index 7494ba91112..d23f19a3240 100644 --- a/include/asm-mips/pgtable-bits.h +++ b/include/asm-mips/pgtable-bits.h @@ -32,7 +32,7 @@ * unpredictable things. The code (when it is written) to deal with * this problem will be in the update_mmu_cache() code for the r4k. */ -#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) #define _PAGE_PRESENT (1<<6) /* implemented in software */ #define _PAGE_READ (1<<7) /* implemented in software */ @@ -122,7 +122,7 @@ #endif #endif -#endif /* defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) */ +#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ #define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) @@ -139,7 +139,7 @@ #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW #endif -#if defined(CONFIG_CPU_MIPS32_R1) && defined(CONFIG_64BIT_PHYS_ADDR) +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) #define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3) #else #define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9) |