diff options
| author | Yoichi Yuasa <yuasa@hh.iij4u.or.jp> | 2005-09-03 15:56:04 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@evo.osdl.org> | 2005-09-05 00:06:02 -0700 |
| commit | 979934da9e7a0005bd9c8b1d7d00febb59ff67f7 (patch) | |
| tree | e42728186c3efaccfa9da1dd2103090846d0c9fc /include/asm-mips/vr41xx | |
| parent | 006cfb51ad12047497a2a5ad796fb8914a1bc487 (diff) | |
[PATCH] mips: update IRQ handling for vr41xx
This patch has updated IRQ handling for vr41xx.
o added common IRQ dispatch
o changed IRQ number in int-handler.S
o added resource management to icu.c
Signed-off-by: Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-mips/vr41xx')
| -rw-r--r-- | include/asm-mips/vr41xx/vr41xx.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/include/asm-mips/vr41xx/vr41xx.h b/include/asm-mips/vr41xx/vr41xx.h index 7d41e44463f..bd2723c3090 100644 --- a/include/asm-mips/vr41xx/vr41xx.h +++ b/include/asm-mips/vr41xx/vr41xx.h @@ -7,7 +7,7 @@ * Copyright (C) 2001, 2002 Paul Mundt * Copyright (C) 2002 MontaVista Software, Inc. * Copyright (C) 2002 TimeSys Corp. - * Copyright (C) 2003-2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> + * Copyright (C) 2003-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp> * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -79,11 +79,11 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock); #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x)) #define MIPS_SOFTINT0_IRQ MIPS_CPU_IRQ(0) #define MIPS_SOFTINT1_IRQ MIPS_CPU_IRQ(1) -#define INT0_CASCADE_IRQ MIPS_CPU_IRQ(2) -#define INT1_CASCADE_IRQ MIPS_CPU_IRQ(3) -#define INT2_CASCADE_IRQ MIPS_CPU_IRQ(4) -#define INT3_CASCADE_IRQ MIPS_CPU_IRQ(5) -#define INT4_CASCADE_IRQ MIPS_CPU_IRQ(6) +#define INT0_IRQ MIPS_CPU_IRQ(2) +#define INT1_IRQ MIPS_CPU_IRQ(3) +#define INT2_IRQ MIPS_CPU_IRQ(4) +#define INT3_IRQ MIPS_CPU_IRQ(5) +#define INT4_IRQ MIPS_CPU_IRQ(6) #define TIMER_IRQ MIPS_CPU_IRQ(7) /* SYINT1 Interrupt Numbers */ @@ -97,7 +97,7 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock); #define PIU_IRQ SYSINT1_IRQ(5) #define AIU_IRQ SYSINT1_IRQ(6) #define KIU_IRQ SYSINT1_IRQ(7) -#define GIUINT_CASCADE_IRQ SYSINT1_IRQ(8) +#define GIUINT_IRQ SYSINT1_IRQ(8) #define SIU_IRQ SYSINT1_IRQ(9) #define BUSERR_IRQ SYSINT1_IRQ(10) #define SOFTINT_IRQ SYSINT1_IRQ(11) @@ -128,7 +128,7 @@ extern void vr41xx_mask_clock(vr41xx_clock_t clock); #define GIU_IRQ_LAST GIU_IRQ(31) extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign); -extern int vr41xx_cascade_irq(unsigned int irq, int (*get_irq_number)(int irq)); +extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *)); #define PIUINT_COMMAND 0x0040 #define PIUINT_DATA 0x0020 |