diff options
| author | Marc St-Jean <stjeanma@pmc-sierra.com> | 2007-06-14 15:55:31 -0600 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-07-10 17:33:03 +0100 |
| commit | 9267a30d1dc7dcd7cadb5eb6a5bbfed703feeefa (patch) | |
| tree | 91fa5a1a4605cdf0a1f1db21e22073b87735ce7a /include/asm-mips/war.h | |
| parent | 35832e26f95ba14a6b6f0519441c5cb64cca6bf9 (diff) | |
[MIPS] PMC MSP71xx mips common
Patch to add mips common support for the PMC-Sierra MSP71xx devices.
Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/war.h')
| -rw-r--r-- | include/asm-mips/war.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index c507f1b8014..45cb8272483 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -198,6 +198,14 @@ #endif /* + * 34K core erratum: "Problems Executing the TLBR Instruction" + */ +#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \ + defined(CONFIG_PMC_MSP7120_FPGA) +#define MIPS34K_MISSED_ITLB_WAR 1 +#endif + +/* * Workarounds default to off */ #ifndef ICACHE_REFILLS_WORKAROUND_WAR @@ -236,5 +244,8 @@ #ifndef R10000_LLSC_WAR #define R10000_LLSC_WAR 0 #endif +#ifndef MIPS34K_MISSED_ITLB_WAR +#define MIPS34K_MISSED_ITLB_WAR 0 +#endif #endif /* _ASM_WAR_H */ |