diff options
author | Anton Altaparmakov <aia21@cantab.net> | 2005-10-30 21:00:04 +0000 |
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committer | Anton Altaparmakov <aia21@cantab.net> | 2005-10-30 21:00:04 +0000 |
commit | 07b188ab773e183871e57b33ae37bf635c9f12ba (patch) | |
tree | 311df8a0dd12fb7bd3e9b5b1a5ca500f0428d679 /include/asm-mips/war.h | |
parent | 47c564e10f219f867bdb49225972749a43485a47 (diff) | |
parent | 9f75e1eff3edb2bb07349b94c28f4f2a6c66ca43 (diff) |
Merge branch 'master' of /usr/src/ntfs-2.6/
Diffstat (limited to 'include/asm-mips/war.h')
-rw-r--r-- | include/asm-mips/war.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index 04ee53b34c2..ad374bd3f13 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h @@ -177,6 +177,17 @@ #endif /* + * The RM9000 has a bug (though PMC-Sierra opposes it being called that) + * where invalid instructions in the same I-cache line worth of instructions + * being fetched may case spurious exceptions. + */ +#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \ + defined(CONFIG_PMC_YOSEMITE) +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#endif + + +/* * ON the R10000 upto version 2.6 (not sure about 2.7) there is a bug that * may cause ll / sc and lld / scd sequences to execute non-atomically. */ @@ -187,6 +198,9 @@ /* * Workarounds default to off */ +#ifndef ICACHE_REFILLS_WORKAROUND_WAR +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#endif #ifndef R4600_V1_INDEX_ICACHEOP_WAR #define R4600_V1_INDEX_ICACHEOP_WAR 0 #endif |