diff options
| author | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2007-02-10 13:45:43 -0600 |
|---|---|---|
| committer | James Bottomley <jejb@mulgrave.il.steeleye.com> | 2007-02-10 13:45:43 -0600 |
| commit | 81b7bbd1932a04869d4c8635a75222dfc6089f96 (patch) | |
| tree | 285ae868a1e3a41fb0dbfe346c28e380949bcb55 /include/asm-powerpc/reg.h | |
| parent | 98051995ab44b993f992946055edc6115351f725 (diff) | |
| parent | 66efc5a7e3061c3597ac43a8bb1026488d57e66b (diff) | |
Merge branch 'linus'
Conflicts:
drivers/scsi/ipr.c
Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'include/asm-powerpc/reg.h')
| -rw-r--r-- | include/asm-powerpc/reg.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h index a3631b15754..0d7f0164ed8 100644 --- a/include/asm-powerpc/reg.h +++ b/include/asm-powerpc/reg.h @@ -166,6 +166,7 @@ #define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */ #define SPRN_SPURR 0x134 /* Scaled PURR */ #define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */ +#define SPRN_LPCR 0x13E /* LPAR Control Register */ #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ @@ -391,6 +392,12 @@ #define SPRN_HSRR0 0x13A /* Save/Restore Register 0 */ #define SPRN_HSRR1 0x13B /* Save/Restore Register 1 */ +#define SPRN_TBCTL 0x35f /* PA6T Timebase control register */ +#define TBCTL_FREEZE 0x0000000000000000ull /* Freeze all tbs */ +#define TBCTL_RESTART 0x0000000100000000ull /* Restart all tbs */ +#define TBCTL_UPDATE_UPPER 0x0000000200000000ull /* Set upper 32 bits */ +#define TBCTL_UPDATE_LOWER 0x0000000300000000ull /* Set lower 32 bits */ + #ifndef SPRN_SVR #define SPRN_SVR 0x11E /* System Version Register */ #endif @@ -462,6 +469,13 @@ #define SPRN_SIAR 780 #define SPRN_SDAR 781 +#define PA6T_SPRN_PMC0 787 +#define PA6T_SPRN_PMC1 788 +#define PA6T_SPRN_PMC2 789 +#define PA6T_SPRN_PMC3 790 +#define PA6T_SPRN_PMC4 791 +#define PA6T_SPRN_PMC5 792 + #else /* 32-bit */ #define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */ #define MMCR0_FC 0x80000000UL /* freeze counters */ |