diff options
| author | David Gibson <david@gibson.dropbear.id.au> | 2006-04-28 15:02:51 +1000 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2006-04-28 15:02:51 +1000 |
| commit | f10a04c034c7285a1b15dfa4a83d3e56578e34e8 (patch) | |
| tree | ee6bd0c670b6606017cbd88b56a1247ff241e00e /include/asm-powerpc | |
| parent | 37e53db8aa233c65142d63b496277bf5be9c0ade (diff) | |
[PATCH] powerpc: Fix pagetable bloat for hugepages
At present, ARCH=powerpc kernels can waste considerable space in
pagetables when making large hugepage mappings. Hugepage PTEs go in
PMD pages, but each PMD page maps 256M and so contains only 16
hugepage PTEs (128 bytes of data), but takes up a 1024 byte
allocation. With CONFIG_PPC_64K_PAGES enabled (64k base page size),
the situation is worse. Now hugepage PTEs are at the PTE page level
(also mapping 256M), so we store 16 hugepage PTEs in a 64k allocation.
The PowerPC MMU already means that any 256M region is either all
hugepage, or all normal pages. Thus, with some care, we can use a
different allocation for the hugepage PTE tables and only allocate the
128 bytes necessary.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include/asm-powerpc')
| -rw-r--r-- | include/asm-powerpc/page_64.h | 1 | ||||
| -rw-r--r-- | include/asm-powerpc/pgalloc.h | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-powerpc/page_64.h b/include/asm-powerpc/page_64.h index 3fb061bab9e..eab779c2199 100644 --- a/include/asm-powerpc/page_64.h +++ b/include/asm-powerpc/page_64.h @@ -101,6 +101,7 @@ extern unsigned int HPAGE_SHIFT; - (1U << GET_HTLB_AREA(addr))) & 0xffff) #define ARCH_HAS_HUGEPAGE_ONLY_RANGE +#define ARCH_HAS_HUGETLB_FREE_PGD_RANGE #define ARCH_HAS_PREPARE_HUGEPAGE_RANGE #define ARCH_HAS_SETCLEAR_HUGE_PTE diff --git a/include/asm-powerpc/pgalloc.h b/include/asm-powerpc/pgalloc.h index a00ee002cd1..9f0917c6865 100644 --- a/include/asm-powerpc/pgalloc.h +++ b/include/asm-powerpc/pgalloc.h @@ -17,11 +17,13 @@ extern kmem_cache_t *pgtable_cache[]; #define PTE_CACHE_NUM 0 #define PMD_CACHE_NUM 1 #define PGD_CACHE_NUM 2 +#define HUGEPTE_CACHE_NUM 3 #else #define PTE_CACHE_NUM 0 #define PMD_CACHE_NUM 1 #define PUD_CACHE_NUM 1 #define PGD_CACHE_NUM 0 +#define HUGEPTE_CACHE_NUM 2 #endif /* |