diff options
| author | Anton Blanchard <anton@samba.org> | 2005-07-07 17:56:11 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2005-07-07 18:23:37 -0700 |
| commit | a2f7a9ce2a5c3d21cc0eb37a03da603b44ba4b09 (patch) | |
| tree | 20d782192f849d9f8f1eabd465246e8fd292324a /include/asm-ppc64 | |
| parent | 315a699851722a6bc31e35f91562f31f55d4c4a2 (diff) | |
[PATCH] ppc64: Fix runlatch code to work on pseries machines
Not all ppc64 CPUs have the CTRL SPR, so we need a cputable feature for it.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include/asm-ppc64')
| -rw-r--r-- | include/asm-ppc64/cputable.h | 3 | ||||
| -rw-r--r-- | include/asm-ppc64/processor.h | 17 |
2 files changed, 13 insertions, 7 deletions
diff --git a/include/asm-ppc64/cputable.h b/include/asm-ppc64/cputable.h index cbbfbec78b6..d67fa9e2607 100644 --- a/include/asm-ppc64/cputable.h +++ b/include/asm-ppc64/cputable.h @@ -138,6 +138,7 @@ extern firmware_feature_t firmware_features_table[]; #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000) #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000) #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000) +#define CPU_FTR_CTRL ASM_CONST(0x0000100000000000) /* Platform firmware features */ #define FW_FTR_ ASM_CONST(0x0000000000000001) @@ -148,7 +149,7 @@ extern firmware_feature_t firmware_features_table[]; #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \ CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \ - CPU_FTR_NODSISRALIGN) + CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL) /* iSeries doesn't support large pages */ #ifdef CONFIG_PPC_ISERIES diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h index af28aa55d8c..06aa07c2c71 100644 --- a/include/asm-ppc64/processor.h +++ b/include/asm-ppc64/processor.h @@ -20,6 +20,7 @@ #include <asm/ptrace.h> #include <asm/types.h> #include <asm/systemcfg.h> +#include <asm/cputable.h> /* Machine State Register (MSR) Fields */ #define MSR_SF_LG 63 /* Enable 64 bit mode */ @@ -501,18 +502,22 @@ static inline void ppc64_runlatch_on(void) { unsigned long ctrl; - ctrl = mfspr(SPRN_CTRLF); - ctrl |= CTRL_RUNLATCH; - mtspr(SPRN_CTRLT, ctrl); + if (cpu_has_feature(CPU_FTR_CTRL)) { + ctrl = mfspr(SPRN_CTRLF); + ctrl |= CTRL_RUNLATCH; + mtspr(SPRN_CTRLT, ctrl); + } } static inline void ppc64_runlatch_off(void) { unsigned long ctrl; - ctrl = mfspr(SPRN_CTRLF); - ctrl &= ~CTRL_RUNLATCH; - mtspr(SPRN_CTRLT, ctrl); + if (cpu_has_feature(CPU_FTR_CTRL)) { + ctrl = mfspr(SPRN_CTRLF); + ctrl &= ~CTRL_RUNLATCH; + mtspr(SPRN_CTRLT, ctrl); + } } #endif /* __KERNEL__ */ |