diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-01-29 08:52:50 +1100 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-01-29 08:52:50 +1100 |
| commit | e189f3495c4e30fc84fc9241096edf3932e23439 (patch) | |
| tree | 5916c89ace81537a02ae01869386ba6caafdab9c /include/asm-sh/cpu-sh4/cache.h | |
| parent | f4798748dee00c807a63f5518f08b3df161e0f6d (diff) | |
| parent | 6582d7b7376aa587d74b08c74457dc28abc1a9fa (diff) | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (197 commits)
sh: add spi header and r2d platform data V3
sh: update r7780rp interrupt code
sh: remove consistent alloc stuff from the machine vector
sh: use declared coherent memory for dreamcast pci ethernet adapter
sh: declared coherent memory support V2
sh: Add support for SDK7780 board.
sh: constify function pointer tables
sh: Kill off -traditional for linker script.
cdrom: Add support for Sega Dreamcast GD-ROM.
sh: Kill off hs7751rvoip reference from arch/sh/Kconfig.
sh: Drop r7780rp_defconfig, use r7780mp_defconfig as kbuild default.
sh: Kill off dead HS771RVoIP board support.
sh: r7785rp: Fix up DECLARE_INTC_DESC() arg mismatch.
sh: r7785rp: Hook up the rest of the HL7785 FPGA IRQ vectors.
sh: r2d - enable sm501 usb host function
sh: remove voyagergx
sh: r2d - add lcd planel timings to sm501 platform data
sh: Add OHCI and UDC platform devices for SH7720.
sh: intc - remove default interrupt priority tables
sh: Correct pte size mismatch for X2 TLB.
...
Diffstat (limited to 'include/asm-sh/cpu-sh4/cache.h')
| -rw-r--r-- | include/asm-sh/cpu-sh4/cache.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/asm-sh/cpu-sh4/cache.h b/include/asm-sh/cpu-sh4/cache.h index f92b20a0983..1c61ebf5c8e 100644 --- a/include/asm-sh/cpu-sh4/cache.h +++ b/include/asm-sh/cpu-sh4/cache.h @@ -12,6 +12,11 @@ #define L1_CACHE_SHIFT 5 +#define SH_CACHE_VALID 1 +#define SH_CACHE_UPDATED 2 +#define SH_CACHE_COMBINED 4 +#define SH_CACHE_ASSOC 8 + #define CCR 0xff00001c /* Address of Cache Control Register */ #define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */ #define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/ |