diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-01-29 08:52:50 +1100 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-01-29 08:52:50 +1100 |
| commit | e189f3495c4e30fc84fc9241096edf3932e23439 (patch) | |
| tree | 5916c89ace81537a02ae01869386ba6caafdab9c /include/asm-sh/cpu-sh4/mmu_context.h | |
| parent | f4798748dee00c807a63f5518f08b3df161e0f6d (diff) | |
| parent | 6582d7b7376aa587d74b08c74457dc28abc1a9fa (diff) | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (197 commits)
sh: add spi header and r2d platform data V3
sh: update r7780rp interrupt code
sh: remove consistent alloc stuff from the machine vector
sh: use declared coherent memory for dreamcast pci ethernet adapter
sh: declared coherent memory support V2
sh: Add support for SDK7780 board.
sh: constify function pointer tables
sh: Kill off -traditional for linker script.
cdrom: Add support for Sega Dreamcast GD-ROM.
sh: Kill off hs7751rvoip reference from arch/sh/Kconfig.
sh: Drop r7780rp_defconfig, use r7780mp_defconfig as kbuild default.
sh: Kill off dead HS771RVoIP board support.
sh: r7785rp: Fix up DECLARE_INTC_DESC() arg mismatch.
sh: r7785rp: Hook up the rest of the HL7785 FPGA IRQ vectors.
sh: r2d - enable sm501 usb host function
sh: remove voyagergx
sh: r2d - add lcd planel timings to sm501 platform data
sh: Add OHCI and UDC platform devices for SH7720.
sh: intc - remove default interrupt priority tables
sh: Correct pte size mismatch for X2 TLB.
...
Diffstat (limited to 'include/asm-sh/cpu-sh4/mmu_context.h')
| -rw-r--r-- | include/asm-sh/cpu-sh4/mmu_context.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/include/asm-sh/cpu-sh4/mmu_context.h b/include/asm-sh/cpu-sh4/mmu_context.h index 979acddc0f8..9ea8eb27b18 100644 --- a/include/asm-sh/cpu-sh4/mmu_context.h +++ b/include/asm-sh/cpu-sh4/mmu_context.h @@ -22,12 +22,20 @@ #define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 #define MMU_PAGE_ASSOC_BIT 0x80 +#define MMUCR_TI (1<<2) + #ifdef CONFIG_X2TLB #define MMUCR_ME (1 << 7) #else #define MMUCR_ME (0) #endif +#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40) +#define MMUCR_SE (1 << 4) +#else +#define MMUCR_SE (0) +#endif + #ifdef CONFIG_SH_STORE_QUEUES #define MMUCR_SQMD (1 << 9) #else @@ -35,7 +43,7 @@ #endif #define MMU_NTLB_ENTRIES 64 -#define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME) +#define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME|MMUCR_SE) #define MMU_ITLB_DATA_ARRAY 0xF3000000 #define MMU_UTLB_DATA_ARRAY 0xF7000000 |