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authorMagnus Damm <damm@igel.co.jp>2007-06-15 18:56:19 +0900
committerPaul Mundt <lethal@linux-sh.org>2007-06-15 18:56:19 +0900
commit68abdbbb03476a60d932eeba0035dd5069afec38 (patch)
treede3854f76d6d9aec121c432a3cd276bb756003c9 /include/asm-sh
parent50f63f2518ee68bc132d357d2b6fdb7f60ef79e0 (diff)
sh: rework ipr code
This patch reworks the ipr code by grouping the offset array together with the ipr_data structure in a new data structure called ipr_desc. This new structure also contains the name of the controller in struct irq_chip. The idea behind putting struct irq_chip in there is that we can use offsetof() to locate the base addresses in the irq_chip callbacks. This strategy has much in common with the recently merged intc2 code. One logic change has been made - the original ipr code enabled the interrupts by default but with this patch they are all disabled by default. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh')
-rw-r--r--include/asm-sh/hw_irq.h23
-rw-r--r--include/asm-sh/irq.h30
-rw-r--r--include/asm-sh/sh03/io.h4
-rw-r--r--include/asm-sh/snapgear.h4
4 files changed, 23 insertions, 38 deletions
diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index f9dfdc04aef..4ca3f765bac 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -24,4 +24,27 @@ struct intc2_desc {
void register_intc2_controller(struct intc2_desc *);
void init_IRQ_intc2(void);
+struct ipr_data {
+ unsigned char irq;
+ unsigned char ipr_idx; /* Index for the IPR registered */
+ unsigned char shift; /* Number of bits to shift the data */
+ unsigned char priority; /* The priority */
+};
+
+struct ipr_desc {
+ unsigned long *ipr_offsets;
+ unsigned int nr_offsets;
+ struct ipr_data *ipr_data;
+ unsigned int nr_irqs;
+ struct irq_chip chip;
+};
+
+void register_ipr_controller(struct ipr_desc *);
+void init_IRQ_ipr(void);
+
+/*
+ * Enable individual interrupt mode for external IPR IRQs.
+ */
+void ipr_irq_enable_irlm(void);
+
#endif /* __ASM_SH_HW_IRQ_H */
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index c247b733a7d..c61d902b8bf 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -31,37 +31,7 @@ extern unsigned short *irq_mask_register;
* PINT IRQs
*/
void init_IRQ_pint(void);
-
-/*
- * The shift value is now the number of bits to shift, not the number of
- * bits/4. This is to make it easier to read the value directly from the
- * datasheets. The IPR address, addr, will be set from ipr_idx via the
- * map_ipridx_to_addr function.
- */
-struct ipr_data {
- unsigned int irq;
- int ipr_idx; /* Index for the IPR registered */
- int shift; /* Number of bits to shift the data */
- int priority; /* The priority */
- unsigned int addr; /* Address of Interrupt Priority Register */
-};
-
-/*
- * Given an IPR IDX, map the value to an IPR register address.
- */
-unsigned int map_ipridx_to_addr(int idx);
-
-/*
- * Enable individual interrupt mode for external IPR IRQs.
- */
-void ipr_irq_enable_irlm(void);
-
-/*
- * Function for "on chip support modules".
- */
-void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
void make_imask_irq(unsigned int irq);
-void init_IRQ_ipr(void);
static inline int generic_irq_demux(int irq)
{
diff --git a/include/asm-sh/sh03/io.h b/include/asm-sh/sh03/io.h
index df3b187ef88..4ff1eb90030 100644
--- a/include/asm-sh/sh03/io.h
+++ b/include/asm-sh/sh03/io.h
@@ -14,22 +14,18 @@
#define INTC_IPRD 0xffd00010UL
#define IRL0_IRQ 2
-#define IRL0_IPR_ADDR INTC_IPRD
#define IRL0_IPR_POS 3
#define IRL0_PRIORITY 13
#define IRL1_IRQ 5
-#define IRL1_IPR_ADDR INTC_IPRD
#define IRL1_IPR_POS 2
#define IRL1_PRIORITY 10
#define IRL2_IRQ 8
-#define IRL2_IPR_ADDR INTC_IPRD
#define IRL2_IPR_POS 1
#define IRL2_PRIORITY 7
#define IRL3_IRQ 11
-#define IRL3_IPR_ADDR INTC_IPRD
#define IRL3_IPR_POS 0
#define IRL3_PRIORITY 4
diff --git a/include/asm-sh/snapgear.h b/include/asm-sh/snapgear.h
index 2d712e72c9e..3554e3a74e9 100644
--- a/include/asm-sh/snapgear.h
+++ b/include/asm-sh/snapgear.h
@@ -20,22 +20,18 @@
*/
#define IRL0_IRQ 2
-#define IRL0_IPR_ADDR INTC_IPRD
#define IRL0_IPR_POS 3
#define IRL0_PRIORITY 13
#define IRL1_IRQ 5
-#define IRL1_IPR_ADDR INTC_IPRD
#define IRL1_IPR_POS 2
#define IRL1_PRIORITY 10
#define IRL2_IRQ 8
-#define IRL2_IPR_ADDR INTC_IPRD
#define IRL2_IPR_POS 1
#define IRL2_PRIORITY 7
#define IRL3_IRQ 11
-#define IRL3_IPR_ADDR INTC_IPRD
#define IRL3_IPR_POS 0
#define IRL3_PRIORITY 4
#endif