diff options
| author | David S. Miller <davem@davemloft.net> | 2008-07-17 23:43:55 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2008-07-17 23:44:53 -0700 |
| commit | f7fe93344fd3f4ccd406a35f751a61b77f94b0fc (patch) | |
| tree | 2d164e040f6acde923147a53e5c92fa0ca0cf0ec /include/asm-sparc/mmu_64.h | |
| parent | d172ad18f9914f70c761a6cad470efc986d5e07e (diff) | |
sparc64: Remove 4MB and 512K base page size options.
Adrian Bunk reported that enabling 4MB page size breaks the build.
The problem is that MAX_ORDER combined with the page shift exceeds the
SECTION_SIZE_BITS we use in asm-sparc64/sparsemem.h
There are several ways I suppose we could work around this. For one
we could define a CONFIG_FORCE_MAX_ZONEORDER to decrease MAX_ORDER in
these higher page size cases.
But I also know that these page size cases are broken wrt. TLB miss
handling especially on pre-hypervisor systems, and there isn't an easy
way to fix that.
These options were meant to be fun experimental hacks anyways, and
only 8K and 64K make any sense to support.
So remove 512K and 4M base page size support. Of course, we still
support these page sizes for huge pages.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/asm-sparc/mmu_64.h')
| -rw-r--r-- | include/asm-sparc/mmu_64.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/include/asm-sparc/mmu_64.h b/include/asm-sparc/mmu_64.h index 8abc58f0f9d..9067dc50053 100644 --- a/include/asm-sparc/mmu_64.h +++ b/include/asm-sparc/mmu_64.h @@ -34,10 +34,6 @@ #define CTX_PGSZ_BASE CTX_PGSZ_8KB #elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB) #define CTX_PGSZ_BASE CTX_PGSZ_64KB -#elif defined(CONFIG_SPARC64_PAGE_SIZE_512KB) -#define CTX_PGSZ_BASE CTX_PGSZ_512KB -#elif defined(CONFIG_SPARC64_PAGE_SIZE_4MB) -#define CTX_PGSZ_BASE CTX_PGSZ_4MB #else #error No page size specified in kernel configuration #endif |