diff options
| author | David S. Miller <davem@davemloft.net> | 2008-07-17 23:43:55 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2008-07-17 23:44:53 -0700 |
| commit | f7fe93344fd3f4ccd406a35f751a61b77f94b0fc (patch) | |
| tree | 2d164e040f6acde923147a53e5c92fa0ca0cf0ec /include/asm-sparc/pgtable_64.h | |
| parent | d172ad18f9914f70c761a6cad470efc986d5e07e (diff) | |
sparc64: Remove 4MB and 512K base page size options.
Adrian Bunk reported that enabling 4MB page size breaks the build.
The problem is that MAX_ORDER combined with the page shift exceeds the
SECTION_SIZE_BITS we use in asm-sparc64/sparsemem.h
There are several ways I suppose we could work around this. For one
we could define a CONFIG_FORCE_MAX_ZONEORDER to decrease MAX_ORDER in
these higher page size cases.
But I also know that these page size cases are broken wrt. TLB miss
handling especially on pre-hypervisor systems, and there isn't an easy
way to fix that.
These options were meant to be fun experimental hacks anyways, and
only 8K and 64K make any sense to support.
So remove 512K and 4M base page size support. Of course, we still
support these page sizes for huge pages.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/asm-sparc/pgtable_64.h')
| -rw-r--r-- | include/asm-sparc/pgtable_64.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/include/asm-sparc/pgtable_64.h b/include/asm-sparc/pgtable_64.h index 78d5594964a..bb9ec2cce35 100644 --- a/include/asm-sparc/pgtable_64.h +++ b/include/asm-sparc/pgtable_64.h @@ -161,12 +161,6 @@ #elif PAGE_SHIFT == 16 #define _PAGE_SZBITS_4U _PAGE_SZ64K_4U #define _PAGE_SZBITS_4V _PAGE_SZ64K_4V -#elif PAGE_SHIFT == 19 -#define _PAGE_SZBITS_4U _PAGE_SZ512K_4U -#define _PAGE_SZBITS_4V _PAGE_SZ512K_4V -#elif PAGE_SHIFT == 22 -#define _PAGE_SZBITS_4U _PAGE_SZ4MB_4U -#define _PAGE_SZBITS_4V _PAGE_SZ4MB_4V #else #error Wrong PAGE_SHIFT specified #endif |