Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6

* master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6:
  [SPARC64]: Update defconfig.
  [SPARC64]: Don't double-export synchronize_irq.
  [SPARC64]: Move over to GENERIC_HARDIRQS.
  [SPARC64]: Virtualize IRQ numbers.
  [SPARC64]: Kill ino_bucket->pil
  [SPARC]: Kill __irq_itoa().
  [SPARC64]: bp->pil can never be zero
  [SPARC64]: Send all device interrupts via one PIL.
  [SPARC]: Fix iommu_flush_iotlb end address
  [SPARC]: Mark smp init functions as cpuinit
  [SPARC]: Add missing rw can_lock macros
  [SPARC]: Setup cpu_possible_map
  [SPARC]: Add topology_init()

5 files changed, 29 insertions, 97 deletions

diff --git a/include/asm-sparc64/cpudata.h b/include/asm-sparc64/cpudata.h
index 9d6a6dbaf12..f2cc9411b4c 100644
--- a/include/asm-sparc64/cpudata.h
+++ b/include/asm-sparc64/cpudata.h
@@ -74,8 +74,10 @@ struct trap_per_cpu {
 	unsigned long		tsb_huge;
 	unsigned long		tsb_huge_temp;
 
-/* Dcache line 8: Unused, needed to keep trap_block a power-of-2 in size.  */
-	unsigned long		__pad2[4];
+/* Dcache line 8: IRQ work list, and keep trap_block a power-of-2 in size.  */
+	unsigned int		irq_worklist;
+	unsigned int		__pad1;
+	unsigned long		__pad2[3];
 } __attribute__((aligned(64)));
 extern struct trap_per_cpu trap_block[NR_CPUS];
 extern void init_cur_cpu_trap(struct thread_info *);
@@ -119,6 +121,7 @@ extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
 #define TRAP_PER_CPU_CPU_LIST_PA	0xc8
 #define TRAP_PER_CPU_TSB_HUGE		0xd0
 #define TRAP_PER_CPU_TSB_HUGE_TEMP	0xd8
+#define TRAP_PER_CPU_IRQ_WORKLIST	0xe0
 
 #define TRAP_BLOCK_SZ_SHIFT		8
 
@@ -171,11 +174,8 @@ extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
 
 /* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
 #define TRAP_LOAD_IRQ_WORK(DEST, TMP)		\
-	__GET_CPUID(TMP)			\
-	sethi	%hi(__irq_work), DEST;		\
-	sllx	TMP, 6, TMP;			\
-	or	DEST, %lo(__irq_work), DEST;	\
-	add	DEST, TMP, DEST;
+	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
+	add	DEST, TRAP_PER_CPU_IRQ_WORKLIST, DEST;
 
 /* Clobbers TMP, loads DEST with current thread info pointer.  */
 #define TRAP_LOAD_THREAD_REG(DEST, TMP)		\
@@ -211,9 +211,10 @@ extern struct sun4v_2insn_patch_entry __sun4v_2insn_patch,
 	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
 	ldx	[DEST + TRAP_PER_CPU_PGD_PADDR], DEST;
 
+/* Clobbers TMP, loads local processor's IRQ work area into DEST.  */
 #define TRAP_LOAD_IRQ_WORK(DEST, TMP)		\
-	sethi	%hi(__irq_work), DEST;		\
-	or	DEST, %lo(__irq_work), DEST;
+	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
+	add	DEST, TRAP_PER_CPU_IRQ_WORKLIST, DEST;
 
 #define TRAP_LOAD_THREAD_REG(DEST, TMP)		\
 	TRAP_LOAD_TRAP_BLOCK(DEST, TMP)		\
diff --git a/include/asm-sparc64/hardirq.h b/include/asm-sparc64/hardirq.h
index f0cf71376ec..7c29fd1a87a 100644
--- a/include/asm-sparc64/hardirq.h
+++ b/include/asm-sparc64/hardirq.h
@@ -12,6 +12,8 @@
 #define local_softirq_pending() \
 	(local_cpu_data().__softirq_pending)
 
+void ack_bad_irq(unsigned int irq);
+
 #define HARDIRQ_BITS	8
 
 #endif /* !(__SPARC64_HARDIRQ_H) */
diff --git a/include/asm-sparc64/hw_irq.h b/include/asm-sparc64/hw_irq.h
index 153cae2ddae..599b3b07345 100644
--- a/include/asm-sparc64/hw_irq.h
+++ b/include/asm-sparc64/hw_irq.h
@@ -1,6 +1,6 @@
 #ifndef __ASM_SPARC64_HW_IRQ_H
 #define __ASM_SPARC64_HW_IRQ_H
 
-/* Dummy include. */
+extern void hw_resend_irq(struct hw_interrupt_type *handler, unsigned int virt_irq);
 
 #endif
diff --git a/include/asm-sparc64/irq.h b/include/asm-sparc64/irq.h
index fa164d37ee3..905e59b4a73 100644
--- a/include/asm-sparc64/irq.h
+++ b/include/asm-sparc64/irq.h
@@ -15,58 +15,6 @@
 #include <asm/pil.h>
 #include <asm/ptrace.h>
 
-struct ino_bucket;
-
-#define MAX_IRQ_DESC_ACTION	4
-
-struct irq_desc {
-	void			(*pre_handler)(struct ino_bucket *, void *, void *);
-	void			*pre_handler_arg1;
-	void			*pre_handler_arg2;
-	u32			action_active_mask;
-	struct irqaction	action[MAX_IRQ_DESC_ACTION];
-};
-
-/* You should not mess with this directly. That's the job of irq.c.
- *
- * If you make changes here, please update hand coded assembler of
- * the vectored interrupt trap handler in entry.S -DaveM
- *
- * This is currently one DCACHE line, two buckets per L2 cache
- * line.  Keep this in mind please.
- */
-struct ino_bucket {
-	/* Next handler in per-CPU PIL worklist.  We know that
-	 * bucket pointers have the high 32-bits clear, so to
-	 * save space we only store the bits we need.
-	 */
-/*0x00*/unsigned int irq_chain;
-
-	/* PIL to schedule this IVEC at. */
-/*0x04*/unsigned char pil;
-
-	/* If an IVEC arrives while irq_info is NULL, we
-	 * set this to notify request_irq() about the event.
-	 */
-/*0x05*/unsigned char pending;
-
-	/* Miscellaneous flags. */
-/*0x06*/unsigned char flags;
-
-	/* Currently unused.  */
-/*0x07*/unsigned char __pad;
-
-	/* Reference to IRQ descriptor for this bucket. */
-/*0x08*/struct irq_desc *irq_info;
-
-	/* Sun5 Interrupt Clear Register. */
-/*0x10*/unsigned long iclr;
-
-	/* Sun5 Interrupt Mapping Register. */
-/*0x18*/unsigned long imap;
-
-};
-
 /* IMAP/ICLR register defines */
 #define IMAP_VALID		0x80000000	/* IRQ Enabled		*/
 #define IMAP_TID_UPA		0x7c000000	/* UPA TargetID		*/
@@ -84,36 +32,20 @@ struct ino_bucket {
 #define ICLR_TRANSMIT		0x00000001	/* Transmit state	*/
 #define ICLR_PENDING		0x00000003	/* Pending state	*/
 
-/* Only 8-bits are available, be careful.  -DaveM */
-#define IBF_PCI		0x02	/* PSYCHO/SABRE/SCHIZO PCI interrupt.	 */
-#define IBF_ACTIVE	0x04	/* Interrupt is active and has a handler.*/
-#define IBF_INPROGRESS	0x10	/* IRQ is being serviced.		 */
-
-#define NUM_IVECS	(IMAP_INR + 1)
-extern struct ino_bucket ivector_table[NUM_IVECS];
-
-#define __irq_ino(irq) \
-        (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
-#define __irq_pil(irq) ((struct ino_bucket *)(unsigned long)(irq))->pil
-#define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
-#define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
-
-static __inline__ char *__irq_itoa(unsigned int irq)
-{
-	static char buff[16];
-
-	sprintf(buff, "%d,%x", __irq_pil(irq), (unsigned int)__irq_ino(irq));
-	return buff;
-}
-
-#define NR_IRQS    16
+/* The largest number of unique interrupt sources we support.
+ * If this needs to ever be larger than 255, you need to change
+ * the type of ino_bucket->virt_irq as appropriate.
+ *
+ * ino_bucket->virt_irq allocation is made during {sun4v_,}build_irq().
+ */
+#define NR_IRQS    255
 
+extern void irq_install_pre_handler(int virt_irq,
+				    void (*func)(unsigned int, void *, void *),
+				    void *arg1, void *arg2);
 #define irq_canonicalize(irq)	(irq)
-extern void disable_irq(unsigned int);
-#define disable_irq_nosync disable_irq
-extern void enable_irq(unsigned int);
-extern unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap);
-extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, int pil, unsigned char flags);
+extern unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap);
+extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino);
 extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
 
 static __inline__ void set_softint(unsigned long bits)
@@ -139,8 +71,4 @@ static __inline__ unsigned long get_softint(void)
 	return retval;
 }
 
-struct irqaction;
-struct pt_regs;
-int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
-
 #endif
diff --git a/include/asm-sparc64/pil.h b/include/asm-sparc64/pil.h
index 79f827eb3f5..72927749aeb 100644
--- a/include/asm-sparc64/pil.h
+++ b/include/asm-sparc64/pil.h
@@ -5,9 +5,9 @@
 /* To avoid some locking problems, we hard allocate certain PILs
  * for SMP cross call messages that must do a etrap/rtrap.
  *
- * A cli() does not block the cross call delivery, so when SMP
- * locking is an issue we reschedule the event into a PIL interrupt
- * which is blocked by cli().
+ * A local_irq_disable() does not block the cross call delivery, so
+ * when SMP locking is an issue we reschedule the event into a PIL
+ * interrupt which is blocked by local_irq_disable().
  *
  * In fact any XCALL which has to etrap/rtrap has a problem because
  * it is difficult to prevent rtrap from running BH's, and that would
@@ -17,6 +17,7 @@
 #define PIL_SMP_RECEIVE_SIGNAL	2
 #define PIL_SMP_CAPTURE		3
 #define PIL_SMP_CTX_NEW_VERSION	4
+#define PIL_DEVICE_IRQ		5
 
 #ifndef __ASSEMBLY__
 #define PIL_RESERVED(PIL)	((PIL) == PIL_SMP_CALL_FUNC || \