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authorSuresh Siddha <suresh.b.siddha@intel.com>2008-09-23 14:00:42 -0700
committerIngo Molnar <mingo@elte.hu>2008-10-10 19:29:17 +0200
commitad5ca55f6bdb47c957b681c7358bb3719ba4ee82 (patch)
tree20ab9e06e840c939da21f6cd352cc5700c9bc9da /include/asm-x86/page.h
parent8311eb84bf842d345f543f4c62ca2b6ea26f638c (diff)
x86, cpa: srlz cpa(), global flush tlb after splitting big page and before doing cpa
Do a global flush tlb after splitting the large page and before we do the actual change page attribute in the PTE. With out this, we violate the TLB application note, which says "The TLBs may contain both ordinary and large-page translations for a 4-KByte range of linear addresses. This may occur if software modifies the paging structures so that the page size used for the address range changes. If the two translations differ with respect to page frame or attributes (e.g., permissions), processor behavior is undefined and may be implementation-specific." And also serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings) using cpa_lock. So that we don't allow any other cpu, with stale large tlb entries change the page attribute in parallel to some other cpu splitting a large page entry along with changing the attribute. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: Suresh Siddha <suresh.b.siddha@intel.com> Cc: arjan@linux.intel.com Cc: venkatesh.pallipadi@intel.com Cc: jeremy@goop.org Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include/asm-x86/page.h')
0 files changed, 0 insertions, 0 deletions