diff options
| author | Jeremy Fitzhardinge <jeremy@goop.org> | 2008-02-04 16:48:02 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-02-04 16:48:02 +0100 |
| commit | f5430f93257d336346a9018c915e879ce43f5f89 (patch) | |
| tree | 77f896b31b405801c6869694fb6c1eccc4b680c1 /include/asm-x86 | |
| parent | edd6bcd8209c31b91e1fbc112a756475091c483d (diff) | |
x86: update reference for PAE tlb flushing
Remove bogus reference to "Pentium-II erratum A13" and point to the
actual canonical source of information about what requirements x86
processors have for PAE pagetable updates.
Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'include/asm-x86')
| -rw-r--r-- | include/asm-x86/pgalloc_32.h | 6 | ||||
| -rw-r--r-- | include/asm-x86/pgtable-3level.h | 6 |
2 files changed, 8 insertions, 4 deletions
diff --git a/include/asm-x86/pgalloc_32.h b/include/asm-x86/pgalloc_32.h index 7641e7b5d93..6c21ef951da 100644 --- a/include/asm-x86/pgalloc_32.h +++ b/include/asm-x86/pgalloc_32.h @@ -80,8 +80,10 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd) set_pud(pudp, __pud(__pa(pmd) | _PAGE_PRESENT)); /* - * Pentium-II erratum A13: in PAE mode we explicitly have to flush - * the TLB via cr3 if the top-level pgd is changed... + * According to Intel App note "TLBs, Paging-Structure Caches, + * and Their Invalidation", April 2007, document 317080-001, + * section 8.1: in PAE mode we explicitly have to flush the + * TLB via cr3 if the top-level pgd is changed... */ if (mm == current->active_mm) write_cr3(read_cr3()); diff --git a/include/asm-x86/pgtable-3level.h b/include/asm-x86/pgtable-3level.h index ad71960bca3..1d763eec740 100644 --- a/include/asm-x86/pgtable-3level.h +++ b/include/asm-x86/pgtable-3level.h @@ -98,8 +98,10 @@ static inline void pud_clear(pud_t *pudp) set_pud(pudp, __pud(0)); /* - * Pentium-II erratum A13: in PAE mode we explicitly have to flush - * the TLB via cr3 if the top-level pgd is changed... + * According to Intel App note "TLBs, Paging-Structure Caches, + * and Their Invalidation", April 2007, document 317080-001, + * section 8.1: in PAE mode we explicitly have to flush the + * TLB via cr3 if the top-level pgd is changed... * * Make sure the pud entry we're updating is within the * current pgd to avoid unnecessary TLB flushes. |