diff options
| author | Michael Turquette <mturquette@linaro.org> | 2014-11-28 21:00:16 -0800 |
|---|---|---|
| committer | Michael Turquette <mturquette@linaro.org> | 2014-11-28 21:00:16 -0800 |
| commit | b572b5f821abb350439609f367bd35961f53a28e (patch) | |
| tree | 380542ae6d32a0f32763062af3194d9628560123 /include/dt-bindings | |
| parent | 250d07d1e782e68e9b2e7b637703b3739f0ec1b1 (diff) | |
| parent | 89bf26cbc1a09476c4c4740d16a0ffdfa2192b9c (diff) | |
Merge tag 'v3.19-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
- clock phase setting capability for the rk3288 mmc clocks
- pll init to allow syncing to actual rate table values
- some more exported clocks
- fixes for some clocks (typos etc) all of them not yet used
in actual drivers
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/rk3288-cru.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index 100a08c4769..f60ce72a2b2 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -71,6 +71,15 @@ #define SCLK_HDMI_CEC 110 #define SCLK_HEVC_CABAC 111 #define SCLK_HEVC_CORE 112 +#define SCLK_I2S0_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO0_DRV 115 +#define SCLK_SDIO1_DRV 116 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO0_SAMPLE 119 +#define SCLK_SDIO1_SAMPLE 120 +#define SCLK_EMMC_SAMPLE 121 #define DCLK_VOP0 190 #define DCLK_VOP1 191 @@ -141,6 +150,10 @@ #define PCLK_VIO2_H2P 361 #define PCLK_CPU 362 #define PCLK_PERI 363 +#define PCLK_DDRUPCTL0 364 +#define PCLK_PUBL0 365 +#define PCLK_DDRUPCTL1 366 +#define PCLK_PUBL1 367 /* hclk gates */ #define HCLK_GPS 448 |