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authorArindam Nath <arindam.nath@amd.com>2011-05-05 12:19:06 +0530
committerChris Ball <cjb@laptop.org>2011-05-24 23:53:48 -0400
commitc3ed3877625f10d600b0eca2ca48a68c46aed660 (patch)
treed8170541551dca7abcefa118c4681d7294e3456d /include/linux/mmc
parent4d55c5a13a189a80d40383f02c8026f9a87d7c87 (diff)
mmc: sdhci: add support for programmable clock mode
Host Controller v3.00 supports programmable clock mode as an optional feature. The support for this mode is indicated by non-zero value in bits 48-55 of the Capabilities register. If supported, the actual value of Clock Multiplier is one more than the value provided in the bit fields. We only set Clock Generator Select (bit 5) and SDCLK Frequency Select (bits 8-15) of the Clock Control register in case Preset Value Enable is not set, otherwise these fields are automatically set by the Host Controller based on the UHS mode selected. Also, since the maximum and minimum clock frequency in this mode can be (Base Clock * Clock Mul) and (Base Clock * Clock Mul)/1024 respectively, f_max and f_min have been recalculated to reflect this change. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
Diffstat (limited to 'include/linux/mmc')
-rw-r--r--include/linux/mmc/sdhci.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index b74c8530e95..a88a799ed7c 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -117,6 +117,7 @@ struct sdhci_host {
unsigned int max_clk; /* Max possible freq (MHz) */
unsigned int timeout_clk; /* Timeout freq (KHz) */
+ unsigned int clk_mul; /* Clock Muliplier value */
unsigned int clock; /* Current clock (MHz) */
u8 pwr; /* Current voltage */