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authorJens Axboe <jaxboe@fusionio.com>2011-03-01 15:04:39 -0500
committerJens Axboe <jaxboe@fusionio.com>2011-03-01 15:04:39 -0500
commit6fae9c25134baffbeeb20031479e7ff6f6d8eec0 (patch)
treec9ab89992ce5293a43cd455a81dc8a5926a28a5e /include/linux/pci_regs.h
parentc186794dbb466b45cf40f942f2d09d6d5b4b0e42 (diff)
parentf5412be599602124d2bdd49947b231dd77c0bf99 (diff)
Merge commit 'v2.6.38-rc6' into for-2.6.39/core
Conflicts: block/cfq-iosched.c Signed-off-by: Jens Axboe <jaxboe@fusionio.com>
Diffstat (limited to 'include/linux/pci_regs.h')
-rw-r--r--include/linux/pci_regs.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index af83076c31a..5b7e6b1ba54 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -309,6 +309,14 @@
#define PCI_MSIX_PBA 8
#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
+/* MSI-X entry's format */
+#define PCI_MSIX_ENTRY_SIZE 16
+#define PCI_MSIX_ENTRY_LOWER_ADDR 0
+#define PCI_MSIX_ENTRY_UPPER_ADDR 4
+#define PCI_MSIX_ENTRY_DATA 8
+#define PCI_MSIX_ENTRY_VECTOR_CTRL 12
+#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
+
/* CompactPCI Hotswap Register */
#define PCI_CHSWP_CSR 2 /* Control and Status Register */
@@ -496,6 +504,8 @@
#define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */
#define PCI_EXP_RTCAP 30 /* Root Capabilities */
#define PCI_EXP_RTSTA 32 /* Root Status */
+#define PCI_EXP_RTSTA_PME 0x10000 /* PME status */
+#define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */
#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */
#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */