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authorMika Westerberg <mika.westerberg@linux.intel.com>2013-01-22 12:26:32 +0200
committerMark Brown <broonie@opensource.wolfsonmicro.com>2013-02-08 13:14:40 +0000
commita0d2642e9296882cda3ad03ff3d9a6649cd70439 (patch)
tree4c3f4a29ba904a357789cd7c2286eb035fa16340 /include/linux/pxa2xx_ssp.h
parentb833172fd8f44fb56e0b3cb810155a6baecc65dc (diff)
spi/pxa2xx: add support for Intel Low Power Subsystem SPI
Intel LPSS SPI is pretty much the same as the PXA27xx SPI except that it has few additional features over the original: o FIFO depth is 256 entries o RX FIFO has one watermark o TX FIFO has two watermarks, low and high o chip select can be controlled by writing to a register The new FIFO registers follow immediately the PXA27xx registers but then there are some additional LPSS private registers at offset 1k or 2k from the base address. For these private registers we add new accessors that take advantage of drv_data->lpss_base once it is resolved. We add a new type LPSS_SSP that can be used to distinguish the LPSS devices from others. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Tested-by: Lu Cao <lucao@marvell.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'include/linux/pxa2xx_ssp.h')
-rw-r--r--include/linux/pxa2xx_ssp.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/include/linux/pxa2xx_ssp.h b/include/linux/pxa2xx_ssp.h
index 065e7f6c3ad..467cc6307b6 100644
--- a/include/linux/pxa2xx_ssp.h
+++ b/include/linux/pxa2xx_ssp.h
@@ -155,6 +155,14 @@
#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
#define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */
+/* LPSS SSP */
+#define SSITF 0x44 /* TX FIFO trigger level */
+#define SSITF_TxLoThresh(x) (((x) - 1) << 8)
+#define SSITF_TxHiThresh(x) ((x) - 1)
+
+#define SSIRF 0x48 /* RX FIFO trigger level */
+#define SSIRF_RxThresh(x) ((x) - 1)
+
enum pxa_ssp_type {
SSP_UNDEFINED = 0,
PXA25x_SSP, /* pxa 210, 250, 255, 26x */
@@ -164,6 +172,7 @@ enum pxa_ssp_type {
PXA168_SSP,
PXA910_SSP,
CE4100_SSP,
+ LPSS_SSP,
};
struct ssp_device {