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authorMika Westerberg <mika.westerberg@linux.intel.com>2013-01-22 12:26:28 +0200
committerMark Brown <broonie@opensource.wolfsonmicro.com>2013-02-08 12:15:21 +0000
commitcd7bed00340475ee72a013a070e200e065085ef3 (patch)
tree98f3cd20ecfaf090a772d0c0b185df7260a8336e /include/linux/spi
parentd560040f7d6fbe0a2990b8f6edca1815e19e72f5 (diff)
spi/pxa2xx: break out the private DMA API usage into a separate file
The PXA SPI driver uses PXA platform specific private DMA implementation which does not work on non-PXA platforms. In order to use this driver on other platforms we break out the private DMA implementation into a separate file that gets compiled only when CONFIG_SPI_PXA2XX_PXADMA is set. The DMA functions are stubbed out if there is no DMA implementation selected (i.e we are building on non-PXA platform). While we are there we can kill the dummy DMA bits in pxa2xx_spi.h as they are not needed anymore for CE4100. Once this is done we can add the generic DMA engine support to the driver that allows usage of any DMA controller that implements DMA engine API. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Lu Cao <lucao@marvell.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'include/linux/spi')
-rw-r--r--include/linux/spi/pxa2xx_spi.h80
1 files changed, 0 insertions, 80 deletions
diff --git a/include/linux/spi/pxa2xx_spi.h b/include/linux/spi/pxa2xx_spi.h
index 053b5ba51b2..d6d2b4d557f 100644
--- a/include/linux/spi/pxa2xx_spi.h
+++ b/include/linux/spi/pxa2xx_spi.h
@@ -53,85 +53,5 @@ struct pxa2xx_spi_chip {
extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info);
-#else
-/*
- * This is the implemtation for CE4100 on x86. ARM defines them in mach/ or
- * plat/ include path.
- * The CE4100 does not provide DMA support. This bits are here to let the driver
- * compile and will never be used. Maybe we get DMA support at a later point in
- * time.
- */
-
-#define DCSR(n) (n)
-#define DSADR(n) (n)
-#define DTADR(n) (n)
-#define DCMD(n) (n)
-#define DRCMR(n) (n)
-
-#define DCSR_RUN (1 << 31) /* Run Bit */
-#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch */
-#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable */
-#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
-#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
-#define DCSR_ENDINTR (1 << 2) /* End Interrupt */
-#define DCSR_STARTINTR (1 << 1) /* Start Interrupt */
-#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt */
-
-#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable */
-#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
-#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
-#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
-#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
-#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
-#define DCSR_EORINTR (1 << 9) /* The end of Receive */
-
-#define DRCMR_MAPVLD (1 << 7) /* Map Valid */
-#define DRCMR_CHLNUM 0x1f /* mask for Channel Number */
-
-#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor */
-#define DDADR_STOP (1 << 0) /* Stop */
-
-#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
-#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
-#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
-#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
-#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
-#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
-#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
-#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
-#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
-#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
-#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
-#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
-#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
-#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
-
-/*
- * Descriptor structure for PXA's DMA engine
- * Note: this structure must always be aligned to a 16-byte boundary.
- */
-
-typedef enum {
- DMA_PRIO_HIGH = 0,
- DMA_PRIO_MEDIUM = 1,
- DMA_PRIO_LOW = 2
-} pxa_dma_prio;
-
-/*
- * DMA registration
- */
-
-static inline int pxa_request_dma(char *name,
- pxa_dma_prio prio,
- void (*irq_handler)(int, void *),
- void *data)
-{
- return -ENODEV;
-}
-
-static inline void pxa_free_dma(int dma_ch)
-{
-}
-
#endif
#endif