diff options
| author | Peter Korsgaard <jacmet@sunsite.dk> | 2011-03-09 17:56:30 +0100 |
|---|---|---|
| committer | Grant Likely <grant.likely@secretlab.ca> | 2011-03-12 01:26:34 -0700 |
| commit | 0b7bb77fd55903ff9dc7c0474c49002aa6b9c78c (patch) | |
| tree | d6f20011adc132700bc3e98d8686cbe838d7c86d /include/linux/spi | |
| parent | 9c3c8afccb6a163fd2be739f511e863eab668702 (diff) | |
gpio/mcp23s08: support mcp23s17 variant
mpc23s17 is very similar to the mcp23s08, except that registers are 16bit
wide, so extend the interface to work with both variants.
The s17 variant also has an additional address pin, so adjust platform
data structure to support up to 8 devices per SPI chipselect.
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'include/linux/spi')
| -rw-r--r-- | include/linux/spi/mcp23s08.h | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/include/linux/spi/mcp23s08.h b/include/linux/spi/mcp23s08.h index 22ef107d770..c42cff8ca19 100644 --- a/include/linux/spi/mcp23s08.h +++ b/include/linux/spi/mcp23s08.h @@ -2,21 +2,24 @@ /* FIXME driver should be able to handle IRQs... */ struct mcp23s08_chip_info { - bool is_present; /* true iff populated */ - u8 pullups; /* BIT(x) means enable pullup x */ + bool is_present; /* true if populated */ + unsigned pullups; /* BIT(x) means enable pullup x */ }; struct mcp23s08_platform_data { - /* Four slaves (numbered 0..3) can share one SPI chipselect, and - * will provide 8..32 GPIOs using 1..4 gpio_chip instances. + /* For mcp23s08, up to 4 slaves (numbered 0..3) can share one SPI + * chipselect, each providing 1 gpio_chip instance with 8 gpios. + * For mpc23s17, up to 8 slaves (numbered 0..7) can share one SPI + * chipselect, each providing 1 gpio_chip (port A + port B) with + * 16 gpios. */ - struct mcp23s08_chip_info chip[4]; + struct mcp23s08_chip_info chip[8]; /* "base" is the number of the first GPIO. Dynamic assignment is * not currently supported, and even if there are gaps in chip * addressing the GPIO numbers are sequential .. so for example * if only slaves 0 and 3 are present, their GPIOs range from - * base to base+15. + * base to base+15 (or base+31 for s17 variant). */ unsigned base; |