diff options
| author | Lad, Prabhakar <prabhakar.csengg@gmail.com> | 2013-05-14 06:45:31 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2013-05-27 09:29:56 -0300 |
| commit | 19ec93057439cffc3b89910cd356892fbe2172fa (patch) | |
| tree | 3f3cec76e640730ea0b9016157d850332dc0a7d9 /include/media | |
| parent | abc0fd734e1327a85306457a438a1a23cf7c7925 (diff) | |
[media] media: i2c: tvp7002: rearrange description of structure members
This patch rearranges the description of field members of
struct tvp7002_config. Also as the all the fields where accepting
a value either 0/1, made the members as bool.
Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'include/media')
| -rw-r--r-- | include/media/tvp7002.h | 44 |
1 files changed, 20 insertions, 24 deletions
diff --git a/include/media/tvp7002.h b/include/media/tvp7002.h index 7123048408d..fadb6afe9ef 100644 --- a/include/media/tvp7002.h +++ b/include/media/tvp7002.h @@ -28,31 +28,27 @@ #define TVP7002_MODULE_NAME "tvp7002" -/* Platform-dependent data - * - * clk_polarity: - * 0 -> data clocked out on rising edge of DATACLK signal - * 1 -> data clocked out on falling edge of DATACLK signal - * hs_polarity: - * 0 -> active low HSYNC output - * 1 -> active high HSYNC output - * sog_polarity: - * 0 -> normal operation - * 1 -> operation with polarity inverted - * vs_polarity: - * 0 -> active low VSYNC output - * 1 -> active high VSYNC output - * fid_polarity: - * 0 -> the field ID output is set to logic 1 for an odd - * field (field 1) and set to logic 0 for an even - * field (field 0). - * 1 -> operation with polarity inverted. +/** + * struct tvp7002_config - Platform dependent data + *@clk_polarity: Clock polarity + * 0 - Data clocked out on rising edge of DATACLK signal + * 1 - Data clocked out on falling edge of DATACLK signal + *@hs_polarity: HSYNC polarity + * 0 - Active low HSYNC output, 1 - Active high HSYNC output + *@vs_polarity: VSYNC Polarity + * 0 - Active low VSYNC output, 1 - Active high VSYNC output + *@fid_polarity: Active-high Field ID polarity. + * 0 - The field ID output is set to logic 1 for an odd field + * (field 1) and set to logic 0 for an even field (field 0). + * 1 - Operation with polarity inverted. + *@sog_polarity: Active high Sync on Green output polarity. + * 0 - Normal operation, 1 - Operation with polarity inverted */ struct tvp7002_config { - u8 clk_polarity; - u8 hs_polarity; - u8 vs_polarity; - u8 fid_polarity; - u8 sog_polarity; + bool clk_polarity; + bool hs_polarity; + bool vs_polarity; + bool fid_polarity; + bool sog_polarity; }; #endif |