diff options
author | Ingo Molnar <mingo@elte.hu> | 2008-10-28 16:26:12 +0100 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2008-10-28 16:26:12 +0100 |
commit | 7a9787e1eba95a166265e6a260cf30af04ef0a99 (patch) | |
tree | e730a4565e0318140d2fbd2f0415d18a339d7336 /include/video | |
parent | 41b9eb264c8407655db57b60b4457fe1b2ec9977 (diff) | |
parent | 0173a3265b228da319ceb9c1ec6a5682fd1b2d92 (diff) |
Merge commit 'v2.6.28-rc2' into x86/pci-ioapic-boot-irq-quirks
Diffstat (limited to 'include/video')
-rw-r--r-- | include/video/atmel_lcdc.h | 4 | ||||
-rw-r--r-- | include/video/cyblafb.h | 2 | ||||
-rw-r--r-- | include/video/ili9320.h | 201 | ||||
-rw-r--r-- | include/video/metronomefb.h | 31 | ||||
-rw-r--r-- | include/video/neomagic.h | 18 | ||||
-rw-r--r-- | include/video/platform_lcd.h | 21 | ||||
-rw-r--r-- | include/video/radeon.h | 32 | ||||
-rw-r--r-- | include/video/s1d13xxxfb.h | 3 | ||||
-rw-r--r-- | include/video/sh_mobile_lcdc.h | 78 | ||||
-rw-r--r-- | include/video/trident.h | 77 |
10 files changed, 368 insertions, 99 deletions
diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h index ed64862c4e1..6ad87f48599 100644 --- a/include/video/atmel_lcdc.h +++ b/include/video/atmel_lcdc.h @@ -22,6 +22,7 @@ #ifndef __ATMEL_LCDC_H__ #define __ATMEL_LCDC_H__ +#include <linux/workqueue.h> /* Way LCD wires are connected to the chip: * Some Atmel chips use BGR color mode (instead of standard RGB) @@ -29,6 +30,7 @@ */ #define ATMEL_LCDC_WIRING_BGR 0 #define ATMEL_LCDC_WIRING_RGB 1 +#define ATMEL_LCDC_WIRING_RGB555 2 /* LCD Controller info data structure, stored in device platform_data */ @@ -37,8 +39,10 @@ struct atmel_lcdfb_info { struct fb_info *info; void __iomem *mmio; unsigned long irq_base; + struct work_struct task; unsigned int guard_time; + unsigned int smem_len; struct platform_device *pdev; struct clk *bus_clk; struct clk *lcdc_clk; diff --git a/include/video/cyblafb.h b/include/video/cyblafb.h index 71744057538..d3c1d4e2c8e 100644 --- a/include/video/cyblafb.h +++ b/include/video/cyblafb.h @@ -4,7 +4,7 @@ #endif #if CYBLAFB_DEBUG -#define debug(f,a...) printk("%s:" f, __FUNCTION__ , ## a); +#define debug(f,a...) printk("%s:" f, __func__ , ## a); #else #define debug(f,a...) #endif diff --git a/include/video/ili9320.h b/include/video/ili9320.h new file mode 100644 index 00000000000..e5d1622e3f3 --- /dev/null +++ b/include/video/ili9320.h @@ -0,0 +1,201 @@ +/* include/video/ili9320.c + * + * ILI9320 LCD controller configuration control. + * + * Copyright 2007 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define ILI9320_REG(x) (x) + +#define ILI9320_INDEX ILI9320_REG(0x00) + +#define ILI9320_OSCILATION ILI9320_REG(0x00) +#define ILI9320_DRIVER ILI9320_REG(0x01) +#define ILI9320_DRIVEWAVE ILI9320_REG(0x02) +#define ILI9320_ENTRYMODE ILI9320_REG(0x03) +#define ILI9320_RESIZING ILI9320_REG(0x04) +#define ILI9320_DISPLAY1 ILI9320_REG(0x07) +#define ILI9320_DISPLAY2 ILI9320_REG(0x08) +#define ILI9320_DISPLAY3 ILI9320_REG(0x09) +#define ILI9320_DISPLAY4 ILI9320_REG(0x0A) +#define ILI9320_RGB_IF1 ILI9320_REG(0x0C) +#define ILI9320_FRAMEMAKER ILI9320_REG(0x0D) +#define ILI9320_RGB_IF2 ILI9320_REG(0x0F) + +#define ILI9320_POWER1 ILI9320_REG(0x10) +#define ILI9320_POWER2 ILI9320_REG(0x11) +#define ILI9320_POWER3 ILI9320_REG(0x12) +#define ILI9320_POWER4 ILI9320_REG(0x13) +#define ILI9320_GRAM_HORIZ_ADDR ILI9320_REG(0x20) +#define ILI9320_GRAM_VERT_ADD ILI9320_REG(0x21) +#define ILI9320_POWER7 ILI9320_REG(0x29) +#define ILI9320_FRAME_RATE_COLOUR ILI9320_REG(0x2B) + +#define ILI9320_GAMMA1 ILI9320_REG(0x30) +#define ILI9320_GAMMA2 ILI9320_REG(0x31) +#define ILI9320_GAMMA3 ILI9320_REG(0x32) +#define ILI9320_GAMMA4 ILI9320_REG(0x35) +#define ILI9320_GAMMA5 ILI9320_REG(0x36) +#define ILI9320_GAMMA6 ILI9320_REG(0x37) +#define ILI9320_GAMMA7 ILI9320_REG(0x38) +#define ILI9320_GAMMA8 ILI9320_REG(0x39) +#define ILI9320_GAMMA9 ILI9320_REG(0x3C) +#define ILI9320_GAMMA10 ILI9320_REG(0x3D) + +#define ILI9320_HORIZ_START ILI9320_REG(0x50) +#define ILI9320_HORIZ_END ILI9320_REG(0x51) +#define ILI9320_VERT_START ILI9320_REG(0x52) +#define ILI9320_VERT_END ILI9320_REG(0x53) + +#define ILI9320_DRIVER2 ILI9320_REG(0x60) +#define ILI9320_BASE_IMAGE ILI9320_REG(0x61) +#define ILI9320_VERT_SCROLL ILI9320_REG(0x6a) + +#define ILI9320_PARTIAL1_POSITION ILI9320_REG(0x80) +#define ILI9320_PARTIAL1_START ILI9320_REG(0x81) +#define ILI9320_PARTIAL1_END ILI9320_REG(0x82) +#define ILI9320_PARTIAL2_POSITION ILI9320_REG(0x83) +#define ILI9320_PARTIAL2_START ILI9320_REG(0x84) +#define ILI9320_PARTIAL2_END ILI9320_REG(0x85) + +#define ILI9320_INTERFACE1 ILI9320_REG(0x90) +#define ILI9320_INTERFACE2 ILI9320_REG(0x92) +#define ILI9320_INTERFACE3 ILI9320_REG(0x93) +#define ILI9320_INTERFACE4 ILI9320_REG(0x95) +#define ILI9320_INTERFACE5 ILI9320_REG(0x97) +#define ILI9320_INTERFACE6 ILI9320_REG(0x98) + +/* Register contents definitions. */ + +#define ILI9320_OSCILATION_OSC (1 << 0) + +#define ILI9320_DRIVER_SS (1 << 8) +#define ILI9320_DRIVER_SM (1 << 10) + +#define ILI9320_DRIVEWAVE_EOR (1 << 8) +#define ILI9320_DRIVEWAVE_BC (1 << 9) +#define ILI9320_DRIVEWAVE_MUSTSET (1 << 10) + +#define ILI9320_ENTRYMODE_AM (1 << 3) +#define ILI9320_ENTRYMODE_ID(x) ((x) << 4) +#define ILI9320_ENTRYMODE_ORG (1 << 7) +#define ILI9320_ENTRYMODE_HWM (1 << 8) +#define ILI9320_ENTRYMODE_BGR (1 << 12) +#define ILI9320_ENTRYMODE_DFM (1 << 14) +#define ILI9320_ENTRYMODE_TRI (1 << 15) + + +#define ILI9320_RESIZING_RSZ(x) ((x) << 0) +#define ILI9320_RESIZING_RCH(x) ((x) << 4) +#define ILI9320_RESIZING_RCV(x) ((x) << 8) + + +#define ILI9320_DISPLAY1_D(x) ((x) << 0) +#define ILI9320_DISPLAY1_CL (1 << 3) +#define ILI9320_DISPLAY1_DTE (1 << 4) +#define ILI9320_DISPLAY1_GON (1 << 5) +#define ILI9320_DISPLAY1_BASEE (1 << 8) +#define ILI9320_DISPLAY1_PTDE(x) ((x) << 12) + + +#define ILI9320_DISPLAY2_BP(x) ((x) << 0) +#define ILI9320_DISPLAY2_FP(x) ((x) << 8) + + +#define ILI9320_RGBIF1_RIM_RGB18 (0 << 0) +#define ILI9320_RGBIF1_RIM_RGB16 (1 << 0) +#define ILI9320_RGBIF1_RIM_RGB6 (2 << 0) + +#define ILI9320_RGBIF1_CLK_INT (0 << 4) +#define ILI9320_RGBIF1_CLK_RGBIF (1 << 4) +#define ILI9320_RGBIF1_CLK_VSYNC (2 << 4) + +#define ILI9320_RGBIF1_RM (1 << 8) + +#define ILI9320_RGBIF1_ENC_FRAMES(x) (((x) - 1)<< 13) + +#define ILI9320_RGBIF2_DPL (1 << 0) +#define ILI9320_RGBIF2_EPL (1 << 1) +#define ILI9320_RGBIF2_HSPL (1 << 3) +#define ILI9320_RGBIF2_VSPL (1 << 4) + + +#define ILI9320_POWER1_SLP (1 << 1) +#define ILI9320_POWER1_DSTB (1 << 2) +#define ILI9320_POWER1_AP(x) ((x) << 4) +#define ILI9320_POWER1_APE (1 << 7) +#define ILI9320_POWER1_BT(x) ((x) << 8) +#define ILI9320_POWER1_SAP (1 << 12) + + +#define ILI9320_POWER2_VC(x) ((x) << 0) +#define ILI9320_POWER2_DC0(x) ((x) << 4) +#define ILI9320_POWER2_DC1(x) ((x) << 8) + + +#define ILI9320_POWER3_VRH(x) ((x) << 0) +#define ILI9320_POWER3_PON (1 << 4) +#define ILI9320_POWER3_VCMR (1 << 8) + + +#define ILI9320_POWER4_VREOUT(x) ((x) << 8) + + +#define ILI9320_DRIVER2_SCNL(x) ((x) << 0) +#define ILI9320_DRIVER2_NL(x) ((x) << 8) +#define ILI9320_DRIVER2_GS (1 << 15) + + +#define ILI9320_BASEIMAGE_REV (1 << 0) +#define ILI9320_BASEIMAGE_VLE (1 << 1) +#define ILI9320_BASEIMAGE_NDL (1 << 2) + + +#define ILI9320_INTERFACE4_RTNE(x) (x) +#define ILI9320_INTERFACE4_DIVE(x) ((x) << 8) + +/* SPI interface definitions */ + +#define ILI9320_SPI_IDCODE (0x70) +#define ILI9320_SPI_ID(x) ((x) << 2) +#define ILI9320_SPI_READ (0x01) +#define ILI9320_SPI_WRITE (0x00) +#define ILI9320_SPI_DATA (0x02) +#define ILI9320_SPI_INDEX (0x00) + +/* platform data to pass configuration from lcd */ + +enum ili9320_suspend { + ILI9320_SUSPEND_OFF, + ILI9320_SUSPEND_DEEP, +}; + +struct ili9320_platdata { + unsigned short hsize; + unsigned short vsize; + + enum ili9320_suspend suspend; + + /* set the reset line, 0 = reset asserted, 1 = normal */ + void (*reset)(unsigned int val); + + unsigned short entry_mode; + unsigned short display2; + unsigned short display3; + unsigned short display4; + unsigned short rgb_if1; + unsigned short rgb_if2; + unsigned short interface2; + unsigned short interface3; + unsigned short interface4; + unsigned short interface5; + unsigned short interface6; +}; + diff --git a/include/video/metronomefb.h b/include/video/metronomefb.h index dab04b4fad7..9863f4b6d41 100644 --- a/include/video/metronomefb.h +++ b/include/video/metronomefb.h @@ -12,14 +12,6 @@ #ifndef _LINUX_METRONOMEFB_H_ #define _LINUX_METRONOMEFB_H_ -/* address and control descriptors used by metronome controller */ -struct metromem_desc { - u32 mFDADR0; - u32 mFSADR0; - u32 mFIDR0; - u32 mLDCMD0; -}; - /* command structure used by metronome controller */ struct metromem_cmd { u16 opcode; @@ -29,34 +21,37 @@ struct metromem_cmd { /* struct used by metronome. board specific stuff comes from *board */ struct metronomefb_par { - unsigned char *metromem; - struct metromem_desc *metromem_desc; struct metromem_cmd *metromem_cmd; unsigned char *metromem_wfm; unsigned char *metromem_img; u16 *metromem_img_csum; u16 *csum_table; - int metromemsize; dma_addr_t metromem_dma; - dma_addr_t metromem_desc_dma; struct fb_info *info; struct metronome_board *board; wait_queue_head_t waitq; u8 frame_count; + int extra_size; + int dt; }; -/* board specific routines */ +/* board specific routines and data */ struct metronome_board { - struct module *owner; - void (*free_irq)(struct fb_info *); - void (*init_gpio_regs)(struct metronomefb_par *); - void (*init_lcdc_regs)(struct metronomefb_par *); - void (*post_dma_setup)(struct metronomefb_par *); + struct module *owner; /* the platform device */ void (*set_rst)(struct metronomefb_par *, int); void (*set_stdby)(struct metronomefb_par *, int); + void (*cleanup)(struct metronomefb_par *); int (*met_wait_event)(struct metronomefb_par *); int (*met_wait_event_intr)(struct metronomefb_par *); int (*setup_irq)(struct fb_info *); + int (*setup_fb)(struct metronomefb_par *); + int (*setup_io)(struct metronomefb_par *); + int (*get_panel_type)(void); + unsigned char *metromem; + int fw; + int fh; + int wfm_size; + struct fb_info *host_fbinfo; /* the host LCD controller's fbi */ }; #endif diff --git a/include/video/neomagic.h b/include/video/neomagic.h index a9e118a1cd1..08b66378295 100644 --- a/include/video/neomagic.h +++ b/include/video/neomagic.h @@ -90,23 +90,6 @@ #define PCI_CHIP_NM2360 0x0006 #define PCI_CHIP_NM2380 0x0016 - -struct xtimings { - unsigned int pixclock; - unsigned int HDisplay; - unsigned int HSyncStart; - unsigned int HSyncEnd; - unsigned int HTotal; - unsigned int VDisplay; - unsigned int VSyncStart; - unsigned int VSyncEnd; - unsigned int VTotal; - unsigned int sync; - int dblscan; - int interlaced; -}; - - /* --------------------------------------------------------------------- */ typedef volatile struct { @@ -140,7 +123,6 @@ typedef volatile struct { struct neofb_par { struct vgastate state; - struct mutex open_lock; unsigned int ref_count; unsigned char MiscOutReg; /* Misc */ diff --git a/include/video/platform_lcd.h b/include/video/platform_lcd.h new file mode 100644 index 00000000000..ad3bdfe743b --- /dev/null +++ b/include/video/platform_lcd.h @@ -0,0 +1,21 @@ +/* include/video/platform_lcd.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * + * Generic platform-device LCD power control interface. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + +struct plat_lcd_data; +struct fb_info; + +struct plat_lcd_data { + void (*set_power)(struct plat_lcd_data *, unsigned int power); + int (*match_fb)(struct plat_lcd_data *, struct fb_info *); +}; + diff --git a/include/video/radeon.h b/include/video/radeon.h index 83467e18f5e..d5dcaf154ba 100644 --- a/include/video/radeon.h +++ b/include/video/radeon.h @@ -386,7 +386,7 @@ #define SC_BOTTOM_RIGHT 0x16F0 #define SRC_SC_BOTTOM_RIGHT 0x16F4 #define RB2D_DSTCACHE_MODE 0x3428 -#define RB2D_DSTCACHE_CTLSTAT 0x342C +#define RB2D_DSTCACHE_CTLSTAT_broken 0x342C /* do not use */ #define LVDS_GEN_CNTL 0x02d0 #define LVDS_PLL_CNTL 0x02d4 #define FP2_GEN_CNTL 0x0288 @@ -525,12 +525,19 @@ #define CRTC_DISPLAY_DIS (1 << 10) #define CRTC_CRT_ON (1 << 15) +/* DSTCACHE_MODE bits constants */ +#define RB2D_DC_AUTOFLUSH_ENABLE (1 << 8) +#define RB2D_DC_DC_DISABLE_IGNORE_PE (1 << 17) /* DSTCACHE_CTLSTAT bit constants */ -#define RB2D_DC_FLUSH (3 << 0) -#define RB2D_DC_FLUSH_ALL 0xf +#define RB2D_DC_FLUSH_2D (1 << 0) +#define RB2D_DC_FREE_2D (1 << 2) +#define RB2D_DC_FLUSH_ALL (RB2D_DC_FLUSH_2D | RB2D_DC_FREE_2D) #define RB2D_DC_BUSY (1 << 31) +/* DSTCACHE_MODE bits constants */ +#define RB2D_DC_AUTOFLUSH_ENABLE (1 << 8) +#define RB2D_DC_DC_DISABLE_IGNORE_PE (1 << 17) /* CRTC_GEN_CNTL bit constants */ #define CRTC_DBL_SCAN_EN 0x00000001 @@ -741,6 +748,10 @@ #define SOFT_RESET_RB (1 << 6) #define SOFT_RESET_HDP (1 << 7) +/* WAIT_UNTIL bit constants */ +#define WAIT_DMA_GUI_IDLE (1 << 9) +#define WAIT_2D_IDLECLEAN (1 << 16) + /* SURFACE_CNTL bit consants */ #define SURF_TRANSLATION_DIS (1 << 8) #define NONSURF_AP0_SWP_16BPP (1 << 20) @@ -858,15 +869,10 @@ #define GMC_DST_16BPP_YVYU422 0x00000c00 #define GMC_DST_32BPP_AYUV444 0x00000e00 #define GMC_DST_16BPP_ARGB4444 0x00000f00 -#define GMC_SRC_MONO 0x00000000 -#define GMC_SRC_MONO_LBKGD 0x00001000 -#define GMC_SRC_DSTCOLOR 0x00003000 #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 #define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 #define GMC_DP_CONVERSION_TEMP_9300 0x00008000 #define GMC_DP_CONVERSION_TEMP_6500 0x00000000 -#define GMC_DP_SRC_RECT 0x02000000 -#define GMC_DP_SRC_HOST 0x03000000 #define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 #define GMC_3D_FCN_EN_CLR 0x00000000 #define GMC_3D_FCN_EN_SET 0x08000000 @@ -877,6 +883,9 @@ #define GMC_WRITE_MASK_LEAVE 0x00000000 #define GMC_WRITE_MASK_SET 0x40000000 #define GMC_CLR_CMP_CNTL_DIS (1 << 28) +#define GMC_SRC_DATATYPE_MASK (3 << 12) +#define GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) +#define GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) #define GMC_SRC_DATATYPE_COLOR (3 << 12) #define ROP3_S 0x00cc0000 #define ROP3_SRCCOPY 0x00cc0000 @@ -885,6 +894,7 @@ #define DP_SRC_SOURCE_MASK (7 << 24) #define GMC_BRUSH_NONE (15 << 4) #define DP_SRC_SOURCE_MEMORY (2 << 24) +#define DP_SRC_SOURCE_HOST_DATA (3 << 24) #define GMC_BRUSH_SOLIDCOLOR 0x000000d0 /* DP_MIX bit constants */ @@ -970,6 +980,12 @@ #define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) #define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) +/* RBBM_GUICNTL constants */ +#define RBBM_GUICNTL_HOST_DATA_SWAP_NONE (0 << 0) +#define RBBM_GUICNTL_HOST_DATA_SWAP_16BIT (1 << 0) +#define RBBM_GUICNTL_HOST_DATA_SWAP_32BIT (2 << 0) +#define RBBM_GUICNTL_HOST_DATA_SWAP_HDW (3 << 0) + /* masks */ #define CONFIG_MEMSIZE_MASK 0x1f000000 diff --git a/include/video/s1d13xxxfb.h b/include/video/s1d13xxxfb.h index c99d261df8f..fe41b840794 100644 --- a/include/video/s1d13xxxfb.h +++ b/include/video/s1d13xxxfb.h @@ -14,7 +14,8 @@ #define S1D13XXXFB_H #define S1D_PALETTE_SIZE 256 -#define S1D_CHIP_REV 7 /* expected chip revision number for s1d13806 */ +#define S1D13506_CHIP_REV 4 /* expected chip revision number for s1d13506 */ +#define S1D13806_CHIP_REV 7 /* expected chip revision number for s1d13806 */ #define S1D_FBID "S1D13806" #define S1D_DEVICENAME "s1d13806fb" diff --git a/include/video/sh_mobile_lcdc.h b/include/video/sh_mobile_lcdc.h new file mode 100644 index 00000000000..1a4bc6ada60 --- /dev/null +++ b/include/video/sh_mobile_lcdc.h @@ -0,0 +1,78 @@ +#ifndef __ASM_SH_MOBILE_LCDC_H__ +#define __ASM_SH_MOBILE_LCDC_H__ + +#include <linux/fb.h> + +enum { RGB8, /* 24bpp, 8:8:8 */ + RGB9, /* 18bpp, 9:9 */ + RGB12A, /* 24bpp, 12:12 */ + RGB12B, /* 12bpp */ + RGB16, /* 16bpp */ + RGB18, /* 18bpp */ + RGB24, /* 24bpp */ + SYS8A, /* 24bpp, 8:8:8 */ + SYS8B, /* 18bpp, 8:8:2 */ + SYS8C, /* 18bpp, 2:8:8 */ + SYS8D, /* 16bpp, 8:8 */ + SYS9, /* 18bpp, 9:9 */ + SYS12, /* 24bpp, 12:12 */ + SYS16A, /* 16bpp */ + SYS16B, /* 18bpp, 16:2 */ + SYS16C, /* 18bpp, 2:16 */ + SYS18, /* 18bpp */ + SYS24 };/* 24bpp */ + +enum { LCDC_CHAN_DISABLED = 0, + LCDC_CHAN_MAINLCD, + LCDC_CHAN_SUBLCD }; + +enum { LCDC_CLK_BUS, LCDC_CLK_PERIPHERAL, LCDC_CLK_EXTERNAL }; + +#define LCDC_FLAGS_DWPOL (1 << 0) /* Rising edge dot clock data latch */ +#define LCDC_FLAGS_DIPOL (1 << 1) /* Active low display enable polarity */ +#define LCDC_FLAGS_DAPOL (1 << 2) /* Active low display data polarity */ +#define LCDC_FLAGS_HSCNT (1 << 3) /* Disable HSYNC during VBLANK */ +#define LCDC_FLAGS_DWCNT (1 << 4) /* Disable dotclock during blanking */ + +struct sh_mobile_lcdc_sys_bus_cfg { + unsigned long ldmt2r; + unsigned long ldmt3r; +}; + +struct sh_mobile_lcdc_sys_bus_ops { + void (*write_index)(void *handle, unsigned long data); + void (*write_data)(void *handle, unsigned long data); + unsigned long (*read_data)(void *handle); +}; + +struct sh_mobile_lcdc_board_cfg { + void *board_data; + int (*setup_sys)(void *board_data, void *sys_ops_handle, + struct sh_mobile_lcdc_sys_bus_ops *sys_ops); + void (*display_on)(void *board_data); + void (*display_off)(void *board_data); +}; + +struct sh_mobile_lcdc_lcd_size_cfg { /* width and height of panel in mm */ + unsigned long width; + unsigned long height; +}; + +struct sh_mobile_lcdc_chan_cfg { + int chan; + int bpp; + int interface_type; /* selects RGBn or SYSn I/F, see above */ + int clock_divider; + unsigned long flags; /* LCDC_FLAGS_... */ + struct fb_videomode lcd_cfg; + struct sh_mobile_lcdc_lcd_size_cfg lcd_size_cfg; + struct sh_mobile_lcdc_board_cfg board_cfg; + struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */ +}; + +struct sh_mobile_lcdc_info { + int clock_source; + struct sh_mobile_lcdc_chan_cfg ch[2]; +}; + +#endif /* __ASM_SH_MOBILE_LCDC_H__ */ diff --git a/include/video/trident.h b/include/video/trident.h index 200be255168..b6ce19d1b61 100644 --- a/include/video/trident.h +++ b/include/video/trident.h @@ -4,9 +4,9 @@ #endif #if TRIDENTFB_DEBUG -#define debug(f,a...) printk("%s:" f, __FUNCTION__ , ## a);mdelay(1000); +#define debug(f, a...) printk("%s:" f, __func__ , ## a); #else -#define debug(f,a...) +#define debug(f, a...) #endif #define output(f, a...) pr_info("tridentfb: " f, ## a) @@ -24,7 +24,9 @@ #define CYBER9397DVD 0x939A #define CYBER9520 0x9520 #define CYBER9525DVD 0x9525 +#define TGUI9440 0x9440 #define TGUI9660 0x9660 +#define PROVIDIA9685 0x9685 #define IMAGE975 0x9750 #define IMAGE985 0x9850 #define BLADE3D 0x9880 @@ -39,36 +41,11 @@ #define CYBERBLADEXPm8 0x9910 #define CYBERBLADEXPm16 0x9930 -/* acceleration families */ -#define IMAGE 0 -#define BLADE 1 -#define XP 2 - -#define is_image(id) -#define is_xp(id) ((id == CYBERBLADEXPAi1) ||\ - (id == CYBERBLADEXPm8) ||\ - (id == CYBERBLADEXPm16)) - -#define is_blade(id) ((id == BLADE3D) ||\ - (id == CYBERBLADEE4) ||\ - (id == CYBERBLADEi7) ||\ - (id == CYBERBLADEi7D) ||\ - (id == CYBERBLADEi1) ||\ - (id == CYBERBLADEi1D) ||\ - (id == CYBERBLADEAi1) ||\ - (id == CYBERBLADEAi1D)) - /* these defines are for 'lcd' variable */ #define LCD_STRETCH 0 #define LCD_CENTER 1 #define LCD_BIOS 2 -/* display types */ -#define DISPLAY_CRT 0 -#define DISPLAY_FP 1 - -#define flatpanel (displaytype == DISPLAY_FP) - /* General Registers */ #define SPR 0x1F /* Software Programming Register (videoram) */ @@ -88,33 +65,7 @@ #define SKey 0x37 #define SPKey 0x57 -/* 0x3x4 */ -#define CRTHTotal 0x00 -#define CRTHDispEnd 0x01 -#define CRTHBlankStart 0x02 -#define CRTHBlankEnd 0x03 -#define CRTHSyncStart 0x04 -#define CRTHSyncEnd 0x05 - -#define CRTVTotal 0x06 -#define CRTVDispEnd 0x12 -#define CRTVBlankStart 0x15 -#define CRTVBlankEnd 0x16 -#define CRTVSyncStart 0x10 -#define CRTVSyncEnd 0x11 - -#define CRTOverflow 0x07 -#define CRTPRowScan 0x08 -#define CRTMaxScanLine 0x09 -#define CRTModeControl 0x17 -#define CRTLineCompare 0x18 - /* 3x4 */ -#define StartAddrHigh 0x0C -#define StartAddrLow 0x0D -#define Offset 0x13 -#define Underline 0x14 -#define CRTCMode 0x17 #define CRTCModuleTest 0x1E #define FIFOControl 0x20 #define LinearAddReg 0x21 @@ -173,3 +124,23 @@ #define BiosMode 0x5c #define BiosReg 0x5d +/* Graphics Engine */ +#define STATUS 0x2120 +#define OLDCMD 0x2124 +#define DRAWFL 0x2128 +#define OLDCLR 0x212C +#define OLDDST 0x2138 +#define OLDSRC 0x213C +#define OLDDIM 0x2140 +#define CMD 0x2144 +#define ROP 0x2148 +#define COLOR 0x2160 +#define BGCOLOR 0x2164 +#define SRC1 0x2100 +#define SRC2 0x2104 +#define DST1 0x2108 +#define DST2 0x210C + +#define ROP_S 0xCC +#define ROP_P 0xF0 +#define ROP_X 0x66 |