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authorRalf Baechle <ralf@linux-mips.org>2006-02-28 17:04:20 +0000
committerRalf Baechle <ralf@linux-mips.org>2006-02-28 17:04:20 +0000
commit778e2ac5970e445f8c6b7d8aa597ac162afe270a (patch)
treedfaa3d0d2732ca14e256f5801a9d91359b70497d /include
parent4debe4f963f9135771a8c5bc66e84396201dcfd8 (diff)
[MIPS] Fix build error on processors that don's support copy-on-write.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-mips/io.h18
1 files changed, 18 insertions, 0 deletions
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
index 5a4c8a54b8f..8c011aa61af 100644
--- a/include/asm-mips/io.h
+++ b/include/asm-mips/io.h
@@ -283,6 +283,24 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
__ioremap_mode((offset), (size), _CACHE_UNCACHED)
/*
+ * ioremap_cachable - map bus memory into CPU space
+ * @offset: bus address of the memory
+ * @size: size of the resource to map
+ *
+ * ioremap_nocache performs a platform specific sequence of operations to
+ * make bus memory CPU accessible via the readb/readw/readl/writeb/
+ * writew/writel functions and the other mmio helpers. The returned
+ * address is not guaranteed to be usable directly as a virtual
+ * address.
+ *
+ * This version of ioremap ensures that the memory is marked cachable by
+ * the CPU. Also enables full write-combining. Useful for some
+ * memory-like regions on I/O busses.
+ */
+#define ioremap_cachable(offset, size) \
+ __ioremap_mode((offset), (size), PAGE_CACHABLE_DEFAULT)
+
+/*
* These two are MIPS specific ioremap variant. ioremap_cacheable_cow
* requests a cachable mapping, ioremap_uncached_accelerated requests a
* mapping using the uncached accelerated mode which isn't supported on