diff options
| author | Richard Kennedy <richard@rsk.demon.co.uk> | 2008-07-04 13:56:16 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-07-04 16:47:19 +0200 |
| commit | 84e65b0a84a2c856bef36f13d122047678408b0a (patch) | |
| tree | 62d2e2e29fa107b3a04cd9156358639ec1e83cd3 /include | |
| parent | 95c60b08c6af6db2165837139da10f593462d51c (diff) | |
x86: cacheline_align tss_struct
The manual padding to align on cacheline size only worked in 32 bit
In 64 bit the structure was not aligned and contained wasted space.
use the compiler ____cachline_aligned to save space & properly align
this structure.
x86_64_default size goes from 9136 -> 8960
x86_64_AMD size goes from 9136 -> 8896
built & running on 2.6.26-rc8.
Signed-off-by: Richard Kennedy <richard@rsk.demon.co.uk>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-x86/processor.h | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h index 559105220a4..4ab2ede6f4b 100644 --- a/include/asm-x86/processor.h +++ b/include/asm-x86/processor.h @@ -263,15 +263,11 @@ struct tss_struct { struct thread_struct *io_bitmap_owner; /* - * Pad the TSS to be cacheline-aligned (size is 0x100): - */ - unsigned long __cacheline_filler[35]; - /* * .. and then another 0x100 bytes for the emergency kernel stack: */ unsigned long stack[64]; -} __attribute__((packed)); +} ____cacheline_aligned; DECLARE_PER_CPU(struct tss_struct, init_tss); |