diff options
| author | Ido Yariv <ido@wizery.com> | 2011-03-31 10:06:57 +0200 |
|---|---|---|
| committer | Luciano Coelho <coelho@ti.com> | 2011-04-19 16:49:17 +0300 |
| commit | d29633b40e6afc6b4276a4e381bc532cc84be104 (patch) | |
| tree | 136e6a871de72b504a8999b924c8c29958654382 /include | |
| parent | 8bf69aae4cb9b196ba5ac386f83a1ca3865af11f (diff) | |
wl12xx: Clean up and fix the 128x boot sequence
Clean up the boot sequence code & fix the following issues:
1. Always read the registers' values and set the relevant bits instead of
zeroing all other bits
2. Handle cases where wl1271_top_reg_read returns an error
3. Verify that the HW can detect the selected clock source
4. Remove 128x PG10 initialization code
5. Configure the MCS PLL to work in HP mode
Signed-off-by: Ido Yariv <ido@wizery.com>
Reviewed-by: Luciano Coelho <coelho@ti.com>
Signed-off-by: Luciano Coelho <coelho@ti.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/wl12xx.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/include/linux/wl12xx.h b/include/linux/wl12xx.h index eb8aacab8d4..c1a743ea747 100644 --- a/include/linux/wl12xx.h +++ b/include/linux/wl12xx.h @@ -26,10 +26,12 @@ /* Reference clock values */ enum { - WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */ - WL12XX_REFCLOCK_26 = 1, /* 26 MHz */ - WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */ - WL12XX_REFCLOCK_54 = 3, /* 54 MHz */ + WL12XX_REFCLOCK_19 = 0, /* 19.2 MHz */ + WL12XX_REFCLOCK_26 = 1, /* 26 MHz */ + WL12XX_REFCLOCK_38 = 2, /* 38.4 MHz */ + WL12XX_REFCLOCK_52 = 3, /* 52 MHz */ + WL12XX_REFCLOCK_38_XTAL = 4, /* 38.4 MHz, XTAL */ + WL12XX_REFCLOCK_26_XTAL = 5, /* 26 MHz, XTAL */ }; /* TCXO clock values */ |