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authorLinus Torvalds <torvalds@linux-foundation.org>2009-04-03 10:36:57 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2009-04-03 10:36:57 -0700
commitca1ee219c070eab755712d50638bbcd1f8630fc1 (patch)
treec0c252a9095830aadc5dc9ffdd16d9167dd605c9 /include
parent3cc50ac0dbda5100684e570247782330155d35e0 (diff)
parentafeeb7cebbd223ffee303fd8de4ba97458b13581 (diff)
Merge git://git.infradead.org/iommu-2.6
* git://git.infradead.org/iommu-2.6: intel-iommu: Fix address wrap on 32-bit kernel. intel-iommu: Enable DMAR on 32-bit kernel. intel-iommu: fix PCI device detach from virtual machine intel-iommu: VT-d page table to support snooping control bit iommu: Add domain_has_cap iommu_ops intel-iommu: Snooping control support Fixed trivial conflicts in arch/x86/Kconfig and drivers/pci/intel-iommu.c
Diffstat (limited to 'include')
-rw-r--r--include/linux/dma_remapping.h1
-rw-r--r--include/linux/intel-iommu.h2
-rw-r--r--include/linux/iommu.h13
3 files changed, 15 insertions, 1 deletions
diff --git a/include/linux/dma_remapping.h b/include/linux/dma_remapping.h
index af1dab41674..1a455f1f86d 100644
--- a/include/linux/dma_remapping.h
+++ b/include/linux/dma_remapping.h
@@ -11,6 +11,7 @@
#define DMA_PTE_READ (1)
#define DMA_PTE_WRITE (2)
+#define DMA_PTE_SNP (1 << 11)
struct intel_iommu;
struct dmar_domain;
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index 1d6c71d96ed..77214ead1a3 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -123,7 +123,7 @@ static inline void dmar_writeq(void __iomem *addr, u64 val)
#define ecap_eim_support(e) ((e >> 4) & 0x1)
#define ecap_ir_support(e) ((e >> 3) & 0x1)
#define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
-
+#define ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping Control */
/* IOTLB_REG */
#define DMA_TLB_FLUSH_GRANU_OFFSET 60
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 8a7bfb1b6ca..3af4ffd591b 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -21,6 +21,7 @@
#define IOMMU_READ (1)
#define IOMMU_WRITE (2)
+#define IOMMU_CACHE (4) /* DMA cache coherency */
struct device;
@@ -28,6 +29,8 @@ struct iommu_domain {
void *priv;
};
+#define IOMMU_CAP_CACHE_COHERENCY 0x1
+
struct iommu_ops {
int (*domain_init)(struct iommu_domain *domain);
void (*domain_destroy)(struct iommu_domain *domain);
@@ -39,6 +42,8 @@ struct iommu_ops {
size_t size);
phys_addr_t (*iova_to_phys)(struct iommu_domain *domain,
unsigned long iova);
+ int (*domain_has_cap)(struct iommu_domain *domain,
+ unsigned long cap);
};
#ifdef CONFIG_IOMMU_API
@@ -57,6 +62,8 @@ extern void iommu_unmap_range(struct iommu_domain *domain, unsigned long iova,
size_t size);
extern phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain,
unsigned long iova);
+extern int iommu_domain_has_cap(struct iommu_domain *domain,
+ unsigned long cap);
#else /* CONFIG_IOMMU_API */
@@ -107,6 +114,12 @@ static inline phys_addr_t iommu_iova_to_phys(struct iommu_domain *domain,
return 0;
}
+static inline int domain_has_cap(struct iommu_domain *domain,
+ unsigned long cap)
+{
+ return 0;
+}
+
#endif /* CONFIG_IOMMU_API */
#endif /* __LINUX_IOMMU_H */