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authorBjorn Helgaas <bhelgaas@google.com>2013-04-17 16:57:56 -0600
committerBjorn Helgaas <bhelgaas@google.com>2013-04-23 09:50:30 -0600
commit703860ed4e36ded696bd44af6107243fdedfb746 (patch)
treeeb5bd366144a03639ac8ae229c571381a1c98e96 /include
parent99369065970e9ea7d1ca489341ed29d1a72ec0b5 (diff)
PCI: Use u8, not int, for PM capability offset
The Power Management Capability (PCI_CAP_ID_PM == 0x01) is defined by PCI and must appear in the 256-byte PCI Configuration Space from 0-0xff. It cannot be in the PCIe Extended Configuration space from 0x100-0xfff, so we only need a u8 to hold its offset. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/pci.h3
1 files changed, 1 insertions, 2 deletions
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 2461033a798..9587d4d1927 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -249,8 +249,7 @@ struct pci_dev {
pci_power_t current_state; /* Current operating state. In ACPI-speak,
this is D0-D3, D0 being fully functional,
and D3 being off. */
- int pm_cap; /* PM capability offset in the
- configuration space */
+ u8 pm_cap; /* PM capability offset */
unsigned int pme_support:5; /* Bitmask of states from which PME#
can be generated */
unsigned int pme_interrupt:1;