diff options
| author | Jaswinder Singh Rajput <jaswinder@kernel.org> | 2009-06-25 18:25:22 +0530 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-06-25 17:30:23 +0200 |
| commit | e5c59547791f171b280bc4c4b2c3ff171824c1a3 (patch) | |
| tree | 6d92559a753fe37655e580e358274ab484ec4c28 /lib/dma-debug.c | |
| parent | 06813f6c743420c16f9248ab59bd2e68a2de57ba (diff) | |
perf_counter tools: Shorten names for events
Added new alias for events.
On AMD box:
$ ./perf stat -e l1d -e l1d-misses -e l1d-write -e l1d-prefetch -e l1d-prefetch-miss -e l1i -e l1i-misses -e l1i-prefetch -e l2 -e l2-misses -e l2-write -e dtlb -e dtlb-misses -e itlb -e itlb-misses -e bpu -e bpu-misses -- ls -lR /usr/include/ > /dev/null
Before :
Performance counter stats for 'ls -lR /usr/include/':
248064467 L1-data-Cache-Load-Referencees (scaled from 23.27%)
1001433 L1-data-Cache-Load-Misses (scaled from 23.34%)
153691 L1-data-Cache-Store-Referencees (scaled from 23.34%)
423248 L1-data-Cache-Prefetch-Referencees (scaled from 23.33%)
302138 L1-data-Cache-Prefetch-Misses (scaled from 23.25%)
251217546 L1-instruction-Cache-Load-Referencees (scaled from 23.25%)
5757005 L1-instruction-Cache-Load-Misses (scaled from 23.23%)
93435 L1-instruction-Cache-Prefetch-Referencees (scaled from 23.24%)
6496073 L2-Cache-Load-Referencees (scaled from 23.32%)
609485 L2-Cache-Load-Misses (scaled from 23.45%)
6876991 L2-Cache-Store-Referencees (scaled from 23.71%)
248922840 Data-TLB-Cache-Load-Referencees (scaled from 23.94%)
5828386 Data-TLB-Cache-Load-Misses (scaled from 24.17%)
257613506 Instruction-TLB-Cache-Load-Referencees (scaled from 24.20%)
6833 Instruction-TLB-Cache-Load-Misses (scaled from 23.88%)
109043606 Branch-Cache-Load-Referencees (scaled from 23.64%)
5552296 Branch-Cache-Load-Misses (scaled from 23.42%)
0.413702461 seconds time elapsed.
After :
Peformance counter stats for 'ls -lR /usr/include/':
266590464 L1-d$-loads (scaled from 23.03%)
1222273 L1-d$-load-misses (scaled from 23.58%)
146204 L1-d$-stores (scaled from 23.83%)
406344 L1-d$-prefetches (scaled from 24.09%)
283748 L1-d$-prefetch-misses (scaled from 24.10%)
249650965 L1-i$-loads (scaled from 23.80%)
3353961 L1-i$-load-misses (scaled from 23.82%)
104599 L1-i$-prefetches (scaled from 23.68%)
4836405 LLC-loads (scaled from 23.67%)
498214 LLC-load-misses (scaled from 23.66%)
4953994 LLC-stores (scaled from 23.64%)
243354097 dTLB-loads (scaled from 23.77%)
6468584 dTLB-load-misses (scaled from 23.74%)
249719549 iTLB-loads (scaled from 23.25%)
5060 iTLB-load-misses (scaled from 23.00%)
112343016 branch-loads (scaled from 22.76%)
5528876 branch-load-misses (scaled from 22.54%)
0.427154051 seconds time elapsed.
Reported-by : Ingo Molnar <mingo@elte.hu>
Signed-off-by: Jaswinder Singh Rajput <jaswinderrajput@gmail.com>
Cc: Peter Zijlstra <peterz@infradead.org>
LKML-Reference: <1245934522.5308.39.camel@hpdv5.satnam>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'lib/dma-debug.c')
0 files changed, 0 insertions, 0 deletions