diff options
| author | Timur Tabi <timur@freescale.com> | 2012-07-23 15:43:32 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2012-07-26 13:26:05 -0500 |
| commit | 896c01cb4bb3cfc2c0ea9873fa7a9f8bd0a7c8d8 (patch) | |
| tree | 8be5534f24ac4b930b1b0b3b43d5ccbf72aa4fc4 /lib/halfmd4.c | |
| parent | 6269f2584a359766f53005c676daff8aee60cbed (diff) | |
powerpc/85xx: p1022ds: fix DIU/LBC switching with NAND enabled
In order for indirect mode on the PIXIS to work properly, both chip selects
need to be set to GPCM mode, otherwise writes to the chip select base
addresses will not actually post to the local bus -- they'll go to the
NAND controller instead. Therefore, we need to set BR0 and BR1 to GPCM
mode before switching to indirect mode.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'lib/halfmd4.c')
0 files changed, 0 insertions, 0 deletions