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authorRuss Anderson <rja@sgi.com>2008-01-03 10:23:49 -0600
committerTony Luck <tony.luck@intel.com>2008-01-03 13:22:54 -0800
commit2022c1f136067f673964dcaffa1cae1008ddcd74 (patch)
treee62db392a3d730156fe8ca62d9e7d507f3e1a8de /lib/parser.c
parent4ca8ad7e4c38cd7f32b11e60418d06fa912a1a37 (diff)
[IA64] Update Altix nofault code
Montecito and Montvale behaves slightly differently than previous Itanium processors, resulting in the MCA due to a failed PIO read to sometimes surfacing outside the nofault code. This code is based on discussions with Intel CPU architects and verified at customer sites. Signed-off-by: Russ Anderson <rja@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
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