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authorDave Airlie <airlied@redhat.com>2010-12-16 14:49:02 +1000
committerDave Airlie <airlied@redhat.com>2010-12-16 14:49:02 +1000
commitca9693a17368041dd5416b0f1f93daaf7a5a5308 (patch)
tree9aaca0a7a535ba6751691b58c54cc226bec91e25 /lib
parentb921bae2eedc806b118a03d986cf0be9ffd3af40 (diff)
parentc45aadabb961501b3e64bc92d0bf12fdce26d37d (diff)
Merge remote branch 'nouveau/drm-nouveau-next' of ../drm-nouveau-next into drm-core-next
* 'nouveau/drm-nouveau-next' of ../drm-nouveau-next: (93 commits) drm/nv50: fix a couple of vm init issues drm/nv04-nv40: Fix up PCI(E) GART DMA object bus address calculation. drm/nouveau: kick vram functions out into an "engine" drm/nouveau: allow gpuobj vinst to be a virtual address when necessary drm/nv50: tidy up PCIEGART implementation drm/nv50: enable non-contig vram allocations where requested drm/nv50: enable 4KiB pages for small vram allocations drm/nv50: implement global channel address space on new VM code drm/nv50: implement BAR1/BAR3 management on top of new VM code drm/nv50: import new vm code drm/nv50: implement custom vram mm drm/nouveau: Avoid potential race between nouveau_fence_update() and context takedown. drm/nouveau: fix use of drm_mm_node in semaphore object drm/nouveau: wrap calls to ttm_bo_validate() drm/nouveau: no need to zero dma objects, we fill them completely anyway drm/nouveau: introduce a util function to wait on reg != val drm/nouveau: implicitly insert non-DMA objects into RAMHT drm/nouveau: make fifo.create_context() responsible for mapping control regs drm/nouveau: Spin for a bit in nouveau_fence_wait() before yielding the CPU. drm/nouveau: Use WC memory on the AGP GART. ...
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