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authorXiubo Li <Li.Xiubo@freescale.com>2013-12-31 15:33:21 +0800
committerMark Brown <broonie@linaro.org>2013-12-31 12:23:10 +0000
commit496a39d9ec238569fac6daceac8f5420c5edc2f1 (patch)
treed69b822dd012c1856a37c0e5b50a382b455b68cf /net/ipv6/esp6.c
parente5d0fa9c3ec59a40e0285d96b65b7f62875acd42 (diff)
ASoC: fsl_sai: Fix one bug for hardware limitation.
This is maybe one bug or a limitation of the hardware that the {T,R}CR2's Synchronous Mode bits must be set as late as possible, or the SAI device maybe hanged up, and there has not any explaination about this limitation in the SAI Data Sheet. And the {T,R}CR2's Synchronous Mode bits must be set at the same time whether for Tx or Rx stream. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'net/ipv6/esp6.c')
0 files changed, 0 insertions, 0 deletions