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authorAntonino A. Daplas <adaplas@gmail.com>2006-06-26 00:26:29 -0700
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-26 09:58:29 -0700
commit3007683144b2d53008363f5a7b36a78c53710db4 (patch)
treedc738feee436ec164fb841f82d015f33e9d36e83 /net
parent22f4a00fd5207a107fb81984f7b4cc09e5047b45 (diff)
[PATCH] fbdev: More accurate sync range extrapolation
The EDID block should specify the display's operating limits (vertical and horizontal sync ranges, and maximum dot clock). If not given by the EDID block, the ranges are extrapolated from the modelist. However, the computation used is only a rough approximation, and the resulting values may not reflect the actual capability of the display. This problem is frequently encountered when the EDID block has a single entry, the single mode entry will fail validation. To prevent this, calculate the values based on the same method used in fb_validate_mode(). Signed-off-by: Antonino Daplas <adaplas@pol.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'net')
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