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authorQipan Li <Qipan.Li@csr.com>2014-04-14 14:29:57 +0800
committerMark Brown <broonie@linaro.org>2014-04-14 21:01:50 +0100
commit818e91625aa17161cd6b39a4d08b77c984f0f485 (patch)
tree1b3d7352466b01abdc09c7581ddcec19507237ce /scripts
parentc9eaa447e77efe77b7fa4c953bd62de8297fd6c5 (diff)
spi: sirf: correct TXFIFO empty interrupt status bit
the old code uses wrong marco - SIRFSOC_SPI_FIFO_FULL is not for FIFO interrupt status, it is for FIFO status. here in the ISR, SIRFSOC_SPI_TXFIFO_EMPTY is the right bit for SPI TXFIFO interrupt status. Signed-off-by: Qipan Li <Qipan.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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