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authorAndrew Jackson <Andrew.Jackson@arm.com>2014-11-07 12:10:44 +0000
committerWolfram Sang <wsa@the-dreams.de>2014-11-21 08:06:32 +0100
commitd39f77b06a712fcba6185a20bb209e357923d980 (patch)
tree96a079b1aec111f9a8c5f526f1197c3ceebbc296 /security/apparmor/policy.c
parent27caca9d2e01c92b26d0690f065aad093fea01c7 (diff)
i2c: designware: prevent early stop on TX FIFO empty
If the Designware core is configured with IC_EMPTYFIFO_HOLD_MASTER_EN set to zero, allowing the TX FIFO to become empty causes a STOP condition to be generated on the I2C bus. If the transmit FIFO threshold is set too high, an erroneous STOP condition can be generated on long transfers - particularly where the interrupt latency is extended. Signed-off-by: Andrew Jackson <Andrew.Jackson@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com> Tested-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'security/apparmor/policy.c')
0 files changed, 0 insertions, 0 deletions