ASoC: tlv320aic3x: Reimplement output mixers

It turned out that the output mixers and their routes were misdefined: They
are not mixing output pins to internal signals but opposite. This has worked
for direct left-to-left and right-to-right routes since for those there are
complete routes. For swapped left-to-right and right-to-left routes this is
not working since there are no routes defined between them.

Another consequence is that those misdefined mixers are incorrectly routed
to several output pins leading unnecessary pin powerings even if there is no
route active to them.

Fix these by reimplementing the output mixers and routes as they are in
hardware. For completeness add also a few missing links between internal
signals and outputs.

Signed-off-by: Jarkko Nikula <jhnikula@gmail.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>

1 files changed, 8 insertions, 0 deletions

diff --git a/sound/soc/codecs/tlv320aic3x.h b/sound/soc/codecs/tlv320aic3x.h
index 20d8cac2637..06a19784b16 100644
--- a/sound/soc/codecs/tlv320aic3x.h
+++ b/sound/soc/codecs/tlv320aic3x.h
@@ -85,22 +85,30 @@
 #define LINE2L_2_HPLOUT_VOL		45
 #define PGAL_2_HPLOUT_VOL		46
 #define DACL1_2_HPLOUT_VOL		47
+#define LINE2R_2_HPLOUT_VOL		48
 #define PGAR_2_HPLOUT_VOL		49
+#define DACR1_2_HPLOUT_VOL		50
 #define HPLOUT_CTRL			51
 /* Left High Power COM control registers */
 #define LINE2L_2_HPLCOM_VOL		52
 #define PGAL_2_HPLCOM_VOL		53
 #define DACL1_2_HPLCOM_VOL		54
+#define LINE2R_2_HPLCOM_VOL		55
 #define PGAR_2_HPLCOM_VOL		56
+#define DACR1_2_HPLCOM_VOL		57
 #define HPLCOM_CTRL			58
 /* Right High Power Output control registers */
+#define LINE2L_2_HPROUT_VOL		59
 #define PGAL_2_HPROUT_VOL		60
+#define DACL1_2_HPROUT_VOL		61
 #define LINE2R_2_HPROUT_VOL		62
 #define PGAR_2_HPROUT_VOL		63
 #define DACR1_2_HPROUT_VOL		64
 #define HPROUT_CTRL			65
 /* Right High Power COM control registers */
+#define LINE2L_2_HPRCOM_VOL		66
 #define PGAL_2_HPRCOM_VOL		67
+#define DACL1_2_HPRCOM_VOL		68
 #define LINE2R_2_HPRCOM_VOL		69
 #define PGAR_2_HPRCOM_VOL		70
 #define DACR1_2_HPRCOM_VOL		71