diff options
| author | Daniel Mack <daniel@caiaq.org> | 2008-11-26 17:47:36 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2008-11-26 18:30:59 +0000 |
| commit | 54f01916297bafc18bd7df4e2300a0544a84fce3 (patch) | |
| tree | 0f4a819087c89004bd059036d7518ed95bedd833 /sound/soc/codecs/tlv320aic3x.h | |
| parent | 414ff491b2ab68359c7a2037b30ccfea20d829d4 (diff) | |
ASoC: Allow more routing features for tlv320aic3x
This patch enables more routing functions for tlv320aic3x codecs.
It is now possible to
- control the volume of the PGA bypass path for the HPL, HPR, HPLCOM
and HPRCOM outputs individually
- route right line1 input to the left ADC channel
- route left line1 input to the right ADC channel
- route right mic3 input to left DAC channel
- route left mic3 input to right DAC channel
- route left line1 input to right line1 output
- route right line1 input to left line1 output
Signed-off-by: Daniel Mack <daniel@caiaq.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/codecs/tlv320aic3x.h')
| -rw-r--r-- | sound/soc/codecs/tlv320aic3x.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/sound/soc/codecs/tlv320aic3x.h b/sound/soc/codecs/tlv320aic3x.h index 00a195aa02e..7e982acf399 100644 --- a/sound/soc/codecs/tlv320aic3x.h +++ b/sound/soc/codecs/tlv320aic3x.h @@ -48,7 +48,9 @@ #define MIC3LR_2_RADC_CTRL 18 /* Line1 Input control registers */ #define LINE1L_2_LADC_CTRL 19 +#define LINE1R_2_LADC_CTRL 21 #define LINE1R_2_RADC_CTRL 22 +#define LINE1L_2_RADC_CTRL 24 /* Line2 Input control registers */ #define LINE2L_2_LADC_CTRL 20 #define LINE2R_2_RADC_CTRL 23 @@ -79,6 +81,8 @@ #define LINE2L_2_HPLOUT_VOL 45 #define LINE2R_2_HPROUT_VOL 62 #define PGAL_2_HPLOUT_VOL 46 +#define PGAL_2_HPROUT_VOL 60 +#define PGAR_2_HPLOUT_VOL 49 #define PGAR_2_HPROUT_VOL 63 #define DACL1_2_HPLOUT_VOL 47 #define DACR1_2_HPROUT_VOL 64 @@ -88,6 +92,8 @@ #define LINE2L_2_HPLCOM_VOL 52 #define LINE2R_2_HPRCOM_VOL 69 #define PGAL_2_HPLCOM_VOL 53 +#define PGAR_2_HPLCOM_VOL 56 +#define PGAL_2_HPRCOM_VOL 67 #define PGAR_2_HPRCOM_VOL 70 #define DACL1_2_HPLCOM_VOL 54 #define DACR1_2_HPRCOM_VOL 71 @@ -103,11 +109,17 @@ #define MONOLOPM_CTRL 79 /* Line Output Plus/Minus control registers */ #define LINE2L_2_LLOPM_VOL 80 +#define LINE2L_2_RLOPM_VOL 87 +#define LINE2R_2_LLOPM_VOL 83 #define LINE2R_2_RLOPM_VOL 90 #define PGAL_2_LLOPM_VOL 81 +#define PGAL_2_RLOPM_VOL 88 +#define PGAR_2_LLOPM_VOL 84 #define PGAR_2_RLOPM_VOL 91 #define DACL1_2_LLOPM_VOL 82 +#define DACL1_2_RLOPM_VOL 89 #define DACR1_2_RLOPM_VOL 92 +#define DACR1_2_LLOPM_VOL 85 #define LLOPM_CTRL 86 #define RLOPM_CTRL 93 /* GPIO/IRQ registers */ |