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authorPeter Ujfalusi <peter.ujfalusi@nokia.com>2010-05-26 11:38:19 +0300
committerLiam Girdwood <lrg@slimlogic.co.uk>2010-05-31 11:08:58 +0100
commit3c36cc688e7ad4ab595a0ac59697e4e1d06338c5 (patch)
tree622be36180386dbad7f19f169cf279249a19c427 /sound/soc/codecs/twl4030.c
parent9fdcc0f72af8801d8429a465a159d815774dbf6d (diff)
ASoC: TWL4030: Correct the ARXR2_APGA_CTL chip default
It seams at least on twl5031 that the ARXR2_APGA_CTL register does not have the same default value as it is written in the TRM. Since the codec part of the PM chip has not been actually changed according to TI, assuming, that all version has the same problem, so writing there the TRM value. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@nokia.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
Diffstat (limited to 'sound/soc/codecs/twl4030.c')
-rw-r--r--sound/soc/codecs/twl4030.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/sound/soc/codecs/twl4030.c b/sound/soc/codecs/twl4030.c
index 30b7bbaf6ae..c667ca5a8a9 100644
--- a/sound/soc/codecs/twl4030.c
+++ b/sound/soc/codecs/twl4030.c
@@ -289,6 +289,9 @@ static void twl4030_init_chip(struct platform_device *pdev)
TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
+ /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
+ twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
+
/* Machine dependent setup */
if (!setup)
return;