diff options
| author | Jonas Andersson <jonas@microbit.se> | 2009-03-04 08:24:26 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2009-03-04 14:47:39 +0000 |
| commit | 86027ae78c9294bb450b76eec28cfb431a8fb3ee (patch) | |
| tree | 4e2634b23e5f050f0065ad4ff2a6845409f1e532 /sound/soc/codecs/wm8510.c | |
| parent | ec67624d33d5639bcc6ee6918cb1fc0bd1bac3a8 (diff) | |
ASoC: wm8510 pll settings
When setting WM8510_MCLKDIV the pll was turned off.
When setting pll frequency you got twice the expected freq, because
the code calculated with postscaler of 8, but the hardware divide by 4.
Signed-off-by: Jonas Andersson <jonas@microbit.se>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound/soc/codecs/wm8510.c')
| -rw-r--r-- | sound/soc/codecs/wm8510.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sound/soc/codecs/wm8510.c b/sound/soc/codecs/wm8510.c index f01078cfbd7..6d4ef71e919 100644 --- a/sound/soc/codecs/wm8510.c +++ b/sound/soc/codecs/wm8510.c @@ -336,7 +336,7 @@ static int wm8510_set_dai_pll(struct snd_soc_dai *codec_dai, return 0; } - pll_factors(freq_out*8, freq_in); + pll_factors(freq_out*4, freq_in); wm8510_write(codec, WM8510_PLLN, (pll_div.pre_div << 4) | pll_div.n); wm8510_write(codec, WM8510_PLLK1, pll_div.k >> 18); @@ -367,7 +367,7 @@ static int wm8510_set_dai_clkdiv(struct snd_soc_dai *codec_dai, wm8510_write(codec, WM8510_GPIO, reg | div); break; case WM8510_MCLKDIV: - reg = wm8510_read_reg_cache(codec, WM8510_CLOCK) & 0x1f; + reg = wm8510_read_reg_cache(codec, WM8510_CLOCK) & 0x11f; wm8510_write(codec, WM8510_CLOCK, reg | div); break; case WM8510_ADCCLK: |