Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6: (250 commits)
  ALSA: hda: Storage class should be before const qualifier
  ASoC: tpa6130a2: Remove CPVSS and HPVdd supplies
  ASoC: tpa6130a2: Define output pins with SND_SOC_DAPM_OUTPUT
  ASoC: sdp4430 - add sdp4430 pcm ops to DAI.
  ASoC: TWL6040: Enable earphone path in codec
  ASoC: SDP4430: Add support for Earphone speaker
  ASoC: SDP4430: Add sdp4430 machine driver
  ASoC: tlv320dac33: Avoid powering off while in BIAS_OFF
  ASoC: tlv320dac33: Use dev_dbg in dac33_hard_power function
  ALSA: sound/pci/asihpi: Use kzalloc
  ALSA: hdmi - dont fail on extra nodes
  ALSA: intelhdmi - add id for the CougarPoint chipset
  ALSA: intelhdmi - user friendly codec name
  ALSA: intelhdmi - add dependency on SND_DYNAMIC_MINORS
  ALSA: asihpi: incorrect range check
  ALSA: asihpi: testing the wrong variable
  ALSA: es1688: add pedantic range checks
  ARM: McBSP: Add support for omap4 in McBSP driver
  ARM: McBSP: Fix request for irq in OMAP4
  OMAP: McBSP: Add 32-bit mode support
  ...

1 files changed, 4 insertions, 217 deletions

diff --git a/sound/soc/codecs/wm8903.h b/sound/soc/codecs/wm8903.h
index 0ea27e2b996..ce384a2ad82 100644
--- a/sound/soc/codecs/wm8903.h
+++ b/sound/soc/codecs/wm8903.h
@@ -18,6 +18,10 @@
 extern struct snd_soc_dai wm8903_dai;
 extern struct snd_soc_codec_device soc_codec_dev_wm8903;
 
+extern int wm8903_mic_detect(struct snd_soc_codec *codec,
+			     struct snd_soc_jack *jack,
+			     int det, int shrt);
+
 #define WM8903_MCLK_DIV_2 1
 #define WM8903_CLK_SYS    2
 #define WM8903_BCLK       3
@@ -173,28 +177,6 @@ extern struct snd_soc_codec_device soc_codec_dev_wm8903;
 #define WM8903_VMID_RES_5K                           4
 
 /*
- * R6 (0x06) - Mic Bias Control 0
- */
-#define WM8903_MICDET_HYST_ENA                  0x0080  /* MICDET_HYST_ENA */
-#define WM8903_MICDET_HYST_ENA_MASK             0x0080  /* MICDET_HYST_ENA */
-#define WM8903_MICDET_HYST_ENA_SHIFT                 7  /* MICDET_HYST_ENA */
-#define WM8903_MICDET_HYST_ENA_WIDTH                 1  /* MICDET_HYST_ENA */
-#define WM8903_MICDET_THR_MASK                  0x0070  /* MICDET_THR - [6:4] */
-#define WM8903_MICDET_THR_SHIFT                      4  /* MICDET_THR - [6:4] */
-#define WM8903_MICDET_THR_WIDTH                      3  /* MICDET_THR - [6:4] */
-#define WM8903_MICSHORT_THR_MASK                0x000C  /* MICSHORT_THR - [3:2] */
-#define WM8903_MICSHORT_THR_SHIFT                    2  /* MICSHORT_THR - [3:2] */
-#define WM8903_MICSHORT_THR_WIDTH                    2  /* MICSHORT_THR - [3:2] */
-#define WM8903_MICDET_ENA                       0x0002  /* MICDET_ENA */
-#define WM8903_MICDET_ENA_MASK                  0x0002  /* MICDET_ENA */
-#define WM8903_MICDET_ENA_SHIFT                      1  /* MICDET_ENA */
-#define WM8903_MICDET_ENA_WIDTH                      1  /* MICDET_ENA */
-#define WM8903_MICBIAS_ENA                      0x0001  /* MICBIAS_ENA */
-#define WM8903_MICBIAS_ENA_MASK                 0x0001  /* MICBIAS_ENA */
-#define WM8903_MICBIAS_ENA_SHIFT                     0  /* MICBIAS_ENA */
-#define WM8903_MICBIAS_ENA_WIDTH                     1  /* MICBIAS_ENA */
-
-/*
  * R8 (0x08) - Analogue DAC 0
  */
 #define WM8903_DACBIAS_SEL_MASK                 0x0018  /* DACBIAS_SEL - [4:3] */
@@ -1135,201 +1117,6 @@ extern struct snd_soc_codec_device soc_codec_dev_wm8903;
 #define WM8903_MASK_WRITE_ENA_WIDTH                  1  /* MASK_WRITE_ENA */
 
 /*
- * R116 (0x74) - GPIO Control 1
- */
-#define WM8903_GP1_FN_MASK                      0x1F00  /* GP1_FN - [12:8] */
-#define WM8903_GP1_FN_SHIFT                          8  /* GP1_FN - [12:8] */
-#define WM8903_GP1_FN_WIDTH                          5  /* GP1_FN - [12:8] */
-#define WM8903_GP1_DIR                          0x0080  /* GP1_DIR */
-#define WM8903_GP1_DIR_MASK                     0x0080  /* GP1_DIR */
-#define WM8903_GP1_DIR_SHIFT                         7  /* GP1_DIR */
-#define WM8903_GP1_DIR_WIDTH                         1  /* GP1_DIR */
-#define WM8903_GP1_OP_CFG                       0x0040  /* GP1_OP_CFG */
-#define WM8903_GP1_OP_CFG_MASK                  0x0040  /* GP1_OP_CFG */
-#define WM8903_GP1_OP_CFG_SHIFT                      6  /* GP1_OP_CFG */
-#define WM8903_GP1_OP_CFG_WIDTH                      1  /* GP1_OP_CFG */
-#define WM8903_GP1_IP_CFG                       0x0020  /* GP1_IP_CFG */
-#define WM8903_GP1_IP_CFG_MASK                  0x0020  /* GP1_IP_CFG */
-#define WM8903_GP1_IP_CFG_SHIFT                      5  /* GP1_IP_CFG */
-#define WM8903_GP1_IP_CFG_WIDTH                      1  /* GP1_IP_CFG */
-#define WM8903_GP1_LVL                          0x0010  /* GP1_LVL */
-#define WM8903_GP1_LVL_MASK                     0x0010  /* GP1_LVL */
-#define WM8903_GP1_LVL_SHIFT                         4  /* GP1_LVL */
-#define WM8903_GP1_LVL_WIDTH                         1  /* GP1_LVL */
-#define WM8903_GP1_PD                           0x0008  /* GP1_PD */
-#define WM8903_GP1_PD_MASK                      0x0008  /* GP1_PD */
-#define WM8903_GP1_PD_SHIFT                          3  /* GP1_PD */
-#define WM8903_GP1_PD_WIDTH                          1  /* GP1_PD */
-#define WM8903_GP1_PU                           0x0004  /* GP1_PU */
-#define WM8903_GP1_PU_MASK                      0x0004  /* GP1_PU */
-#define WM8903_GP1_PU_SHIFT                          2  /* GP1_PU */
-#define WM8903_GP1_PU_WIDTH                          1  /* GP1_PU */
-#define WM8903_GP1_INTMODE                      0x0002  /* GP1_INTMODE */
-#define WM8903_GP1_INTMODE_MASK                 0x0002  /* GP1_INTMODE */
-#define WM8903_GP1_INTMODE_SHIFT                     1  /* GP1_INTMODE */
-#define WM8903_GP1_INTMODE_WIDTH                     1  /* GP1_INTMODE */
-#define WM8903_GP1_DB                           0x0001  /* GP1_DB */
-#define WM8903_GP1_DB_MASK                      0x0001  /* GP1_DB */
-#define WM8903_GP1_DB_SHIFT                          0  /* GP1_DB */
-#define WM8903_GP1_DB_WIDTH                          1  /* GP1_DB */
-
-/*
- * R117 (0x75) - GPIO Control 2
- */
-#define WM8903_GP2_FN_MASK                      0x1F00  /* GP2_FN - [12:8] */
-#define WM8903_GP2_FN_SHIFT                          8  /* GP2_FN - [12:8] */
-#define WM8903_GP2_FN_WIDTH                          5  /* GP2_FN - [12:8] */
-#define WM8903_GP2_DIR                          0x0080  /* GP2_DIR */
-#define WM8903_GP2_DIR_MASK                     0x0080  /* GP2_DIR */
-#define WM8903_GP2_DIR_SHIFT                         7  /* GP2_DIR */
-#define WM8903_GP2_DIR_WIDTH                         1  /* GP2_DIR */
-#define WM8903_GP2_OP_CFG                       0x0040  /* GP2_OP_CFG */
-#define WM8903_GP2_OP_CFG_MASK                  0x0040  /* GP2_OP_CFG */
-#define WM8903_GP2_OP_CFG_SHIFT                      6  /* GP2_OP_CFG */
-#define WM8903_GP2_OP_CFG_WIDTH                      1  /* GP2_OP_CFG */
-#define WM8903_GP2_IP_CFG                       0x0020  /* GP2_IP_CFG */
-#define WM8903_GP2_IP_CFG_MASK                  0x0020  /* GP2_IP_CFG */
-#define WM8903_GP2_IP_CFG_SHIFT                      5  /* GP2_IP_CFG */
-#define WM8903_GP2_IP_CFG_WIDTH                      1  /* GP2_IP_CFG */
-#define WM8903_GP2_LVL                          0x0010  /* GP2_LVL */
-#define WM8903_GP2_LVL_MASK                     0x0010  /* GP2_LVL */
-#define WM8903_GP2_LVL_SHIFT                         4  /* GP2_LVL */
-#define WM8903_GP2_LVL_WIDTH                         1  /* GP2_LVL */
-#define WM8903_GP2_PD                           0x0008  /* GP2_PD */
-#define WM8903_GP2_PD_MASK                      0x0008  /* GP2_PD */
-#define WM8903_GP2_PD_SHIFT                          3  /* GP2_PD */
-#define WM8903_GP2_PD_WIDTH                          1  /* GP2_PD */
-#define WM8903_GP2_PU                           0x0004  /* GP2_PU */
-#define WM8903_GP2_PU_MASK                      0x0004  /* GP2_PU */
-#define WM8903_GP2_PU_SHIFT                          2  /* GP2_PU */
-#define WM8903_GP2_PU_WIDTH                          1  /* GP2_PU */
-#define WM8903_GP2_INTMODE                      0x0002  /* GP2_INTMODE */
-#define WM8903_GP2_INTMODE_MASK                 0x0002  /* GP2_INTMODE */
-#define WM8903_GP2_INTMODE_SHIFT                     1  /* GP2_INTMODE */
-#define WM8903_GP2_INTMODE_WIDTH                     1  /* GP2_INTMODE */
-#define WM8903_GP2_DB                           0x0001  /* GP2_DB */
-#define WM8903_GP2_DB_MASK                      0x0001  /* GP2_DB */
-#define WM8903_GP2_DB_SHIFT                          0  /* GP2_DB */
-#define WM8903_GP2_DB_WIDTH                          1  /* GP2_DB */
-
-/*
- * R118 (0x76) - GPIO Control 3
- */
-#define WM8903_GP3_FN_MASK                      0x1F00  /* GP3_FN - [12:8] */
-#define WM8903_GP3_FN_SHIFT                          8  /* GP3_FN - [12:8] */
-#define WM8903_GP3_FN_WIDTH                          5  /* GP3_FN - [12:8] */
-#define WM8903_GP3_DIR                          0x0080  /* GP3_DIR */
-#define WM8903_GP3_DIR_MASK                     0x0080  /* GP3_DIR */
-#define WM8903_GP3_DIR_SHIFT                         7  /* GP3_DIR */
-#define WM8903_GP3_DIR_WIDTH                         1  /* GP3_DIR */
-#define WM8903_GP3_OP_CFG                       0x0040  /* GP3_OP_CFG */
-#define WM8903_GP3_OP_CFG_MASK                  0x0040  /* GP3_OP_CFG */
-#define WM8903_GP3_OP_CFG_SHIFT                      6  /* GP3_OP_CFG */
-#define WM8903_GP3_OP_CFG_WIDTH                      1  /* GP3_OP_CFG */
-#define WM8903_GP3_IP_CFG                       0x0020  /* GP3_IP_CFG */
-#define WM8903_GP3_IP_CFG_MASK                  0x0020  /* GP3_IP_CFG */
-#define WM8903_GP3_IP_CFG_SHIFT                      5  /* GP3_IP_CFG */
-#define WM8903_GP3_IP_CFG_WIDTH                      1  /* GP3_IP_CFG */
-#define WM8903_GP3_LVL                          0x0010  /* GP3_LVL */
-#define WM8903_GP3_LVL_MASK                     0x0010  /* GP3_LVL */
-#define WM8903_GP3_LVL_SHIFT                         4  /* GP3_LVL */
-#define WM8903_GP3_LVL_WIDTH                         1  /* GP3_LVL */
-#define WM8903_GP3_PD                           0x0008  /* GP3_PD */
-#define WM8903_GP3_PD_MASK                      0x0008  /* GP3_PD */
-#define WM8903_GP3_PD_SHIFT                          3  /* GP3_PD */
-#define WM8903_GP3_PD_WIDTH                          1  /* GP3_PD */
-#define WM8903_GP3_PU                           0x0004  /* GP3_PU */
-#define WM8903_GP3_PU_MASK                      0x0004  /* GP3_PU */
-#define WM8903_GP3_PU_SHIFT                          2  /* GP3_PU */
-#define WM8903_GP3_PU_WIDTH                          1  /* GP3_PU */
-#define WM8903_GP3_INTMODE                      0x0002  /* GP3_INTMODE */
-#define WM8903_GP3_INTMODE_MASK                 0x0002  /* GP3_INTMODE */
-#define WM8903_GP3_INTMODE_SHIFT                     1  /* GP3_INTMODE */
-#define WM8903_GP3_INTMODE_WIDTH                     1  /* GP3_INTMODE */
-#define WM8903_GP3_DB                           0x0001  /* GP3_DB */
-#define WM8903_GP3_DB_MASK                      0x0001  /* GP3_DB */
-#define WM8903_GP3_DB_SHIFT                          0  /* GP3_DB */
-#define WM8903_GP3_DB_WIDTH                          1  /* GP3_DB */
-
-/*
- * R119 (0x77) - GPIO Control 4
- */
-#define WM8903_GP4_FN_MASK                      0x1F00  /* GP4_FN - [12:8] */
-#define WM8903_GP4_FN_SHIFT                          8  /* GP4_FN - [12:8] */
-#define WM8903_GP4_FN_WIDTH                          5  /* GP4_FN - [12:8] */
-#define WM8903_GP4_DIR                          0x0080  /* GP4_DIR */
-#define WM8903_GP4_DIR_MASK                     0x0080  /* GP4_DIR */
-#define WM8903_GP4_DIR_SHIFT                         7  /* GP4_DIR */
-#define WM8903_GP4_DIR_WIDTH                         1  /* GP4_DIR */
-#define WM8903_GP4_OP_CFG                       0x0040  /* GP4_OP_CFG */
-#define WM8903_GP4_OP_CFG_MASK                  0x0040  /* GP4_OP_CFG */
-#define WM8903_GP4_OP_CFG_SHIFT                      6  /* GP4_OP_CFG */
-#define WM8903_GP4_OP_CFG_WIDTH                      1  /* GP4_OP_CFG */
-#define WM8903_GP4_IP_CFG                       0x0020  /* GP4_IP_CFG */
-#define WM8903_GP4_IP_CFG_MASK                  0x0020  /* GP4_IP_CFG */
-#define WM8903_GP4_IP_CFG_SHIFT                      5  /* GP4_IP_CFG */
-#define WM8903_GP4_IP_CFG_WIDTH                      1  /* GP4_IP_CFG */
-#define WM8903_GP4_LVL                          0x0010  /* GP4_LVL */
-#define WM8903_GP4_LVL_MASK                     0x0010  /* GP4_LVL */
-#define WM8903_GP4_LVL_SHIFT                         4  /* GP4_LVL */
-#define WM8903_GP4_LVL_WIDTH                         1  /* GP4_LVL */
-#define WM8903_GP4_PD                           0x0008  /* GP4_PD */
-#define WM8903_GP4_PD_MASK                      0x0008  /* GP4_PD */
-#define WM8903_GP4_PD_SHIFT                          3  /* GP4_PD */
-#define WM8903_GP4_PD_WIDTH                          1  /* GP4_PD */
-#define WM8903_GP4_PU                           0x0004  /* GP4_PU */
-#define WM8903_GP4_PU_MASK                      0x0004  /* GP4_PU */
-#define WM8903_GP4_PU_SHIFT                          2  /* GP4_PU */
-#define WM8903_GP4_PU_WIDTH                          1  /* GP4_PU */
-#define WM8903_GP4_INTMODE                      0x0002  /* GP4_INTMODE */
-#define WM8903_GP4_INTMODE_MASK                 0x0002  /* GP4_INTMODE */
-#define WM8903_GP4_INTMODE_SHIFT                     1  /* GP4_INTMODE */
-#define WM8903_GP4_INTMODE_WIDTH                     1  /* GP4_INTMODE */
-#define WM8903_GP4_DB                           0x0001  /* GP4_DB */
-#define WM8903_GP4_DB_MASK                      0x0001  /* GP4_DB */
-#define WM8903_GP4_DB_SHIFT                          0  /* GP4_DB */
-#define WM8903_GP4_DB_WIDTH                          1  /* GP4_DB */
-
-/*
- * R120 (0x78) - GPIO Control 5
- */
-#define WM8903_GP5_FN_MASK                      0x1F00  /* GP5_FN - [12:8] */
-#define WM8903_GP5_FN_SHIFT                          8  /* GP5_FN - [12:8] */
-#define WM8903_GP5_FN_WIDTH                          5  /* GP5_FN - [12:8] */
-#define WM8903_GP5_DIR                          0x0080  /* GP5_DIR */
-#define WM8903_GP5_DIR_MASK                     0x0080  /* GP5_DIR */
-#define WM8903_GP5_DIR_SHIFT                         7  /* GP5_DIR */
-#define WM8903_GP5_DIR_WIDTH                         1  /* GP5_DIR */
-#define WM8903_GP5_OP_CFG                       0x0040  /* GP5_OP_CFG */
-#define WM8903_GP5_OP_CFG_MASK                  0x0040  /* GP5_OP_CFG */
-#define WM8903_GP5_OP_CFG_SHIFT                      6  /* GP5_OP_CFG */
-#define WM8903_GP5_OP_CFG_WIDTH                      1  /* GP5_OP_CFG */
-#define WM8903_GP5_IP_CFG                       0x0020  /* GP5_IP_CFG */
-#define WM8903_GP5_IP_CFG_MASK                  0x0020  /* GP5_IP_CFG */
-#define WM8903_GP5_IP_CFG_SHIFT                      5  /* GP5_IP_CFG */
-#define WM8903_GP5_IP_CFG_WIDTH                      1  /* GP5_IP_CFG */
-#define WM8903_GP5_LVL                          0x0010  /* GP5_LVL */
-#define WM8903_GP5_LVL_MASK                     0x0010  /* GP5_LVL */
-#define WM8903_GP5_LVL_SHIFT                         4  /* GP5_LVL */
-#define WM8903_GP5_LVL_WIDTH                         1  /* GP5_LVL */
-#define WM8903_GP5_PD                           0x0008  /* GP5_PD */
-#define WM8903_GP5_PD_MASK                      0x0008  /* GP5_PD */
-#define WM8903_GP5_PD_SHIFT                          3  /* GP5_PD */
-#define WM8903_GP5_PD_WIDTH                          1  /* GP5_PD */
-#define WM8903_GP5_PU                           0x0004  /* GP5_PU */
-#define WM8903_GP5_PU_MASK                      0x0004  /* GP5_PU */
-#define WM8903_GP5_PU_SHIFT                          2  /* GP5_PU */
-#define WM8903_GP5_PU_WIDTH                          1  /* GP5_PU */
-#define WM8903_GP5_INTMODE                      0x0002  /* GP5_INTMODE */
-#define WM8903_GP5_INTMODE_MASK                 0x0002  /* GP5_INTMODE */
-#define WM8903_GP5_INTMODE_SHIFT                     1  /* GP5_INTMODE */
-#define WM8903_GP5_INTMODE_WIDTH                     1  /* GP5_INTMODE */
-#define WM8903_GP5_DB                           0x0001  /* GP5_DB */
-#define WM8903_GP5_DB_MASK                      0x0001  /* GP5_DB */
-#define WM8903_GP5_DB_SHIFT                          0  /* GP5_DB */
-#define WM8903_GP5_DB_WIDTH                          1  /* GP5_DB */
-
-/*
  * R121 (0x79) - Interrupt Status 1
  */
 #define WM8903_MICSHRT_EINT                     0x8000  /* MICSHRT_EINT */