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authorStephen Warren <swarren@nvidia.com>2011-07-01 13:56:13 -0600
committerMark Brown <broonie@opensource.wolfsonmicro.com>2011-07-04 08:49:05 -0700
commit713d1369789f2a2336c3431b15276c968862bdb7 (patch)
treef6949f9aa9747176596453c8ce0e453e71abf4c1 /sound
parente999dc50404d401150a5429b6459473a691fd1a0 (diff)
ASoC: Tegra: I2S: Ensure clock is enabled when writing regs
The I2S controller needs a clock to respond to register writes. Without this, register writes will at worst hang the CPU. In practice, I've only observed writes being dropped. Luckily, the dropped register writes historically had no effect: TEGRA_I2S_TIMING: The value we wrote was the reset default. TEGRA_I2S_FIFO_SCR: The default was for the FIFOs to request more data when one slot was empty. The requested value was for the FIFOs to request when four slots were empty. The DMA controller in the mainline kernel is configured to burst a single entry at a time into the FIFO, hence there was no issue. The only negative effect was on bus efficiency losses due to an increased number of arbitration attempts. However, in various non-upstream changes, the DMA controller now bursts four entries at a time into the FIFO. If there is only space for one entry, the data is simply dropped. In practice, this resulted in 3/4 of samples being dropped, and playback at 4x the expected rate and pitch. By fixing the clocking issue, this is solved. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound')
-rw-r--r--sound/soc/tegra/tegra_i2s.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/sound/soc/tegra/tegra_i2s.c b/sound/soc/tegra/tegra_i2s.c
index 6b817e20548..95f03c10b4f 100644
--- a/sound/soc/tegra/tegra_i2s.c
+++ b/sound/soc/tegra/tegra_i2s.c
@@ -222,12 +222,18 @@ static int tegra_i2s_hw_params(struct snd_pcm_substream *substream,
if (i2sclock % (2 * srate))
reg |= TEGRA_I2S_TIMING_NON_SYM_ENABLE;
+ if (!i2s->clk_refs)
+ clk_enable(i2s->clk_i2s);
+
tegra_i2s_write(i2s, TEGRA_I2S_TIMING, reg);
tegra_i2s_write(i2s, TEGRA_I2S_FIFO_SCR,
TEGRA_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS |
TEGRA_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS);
+ if (!i2s->clk_refs)
+ clk_disable(i2s->clk_i2s);
+
return 0;
}