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authorMarek Belisko <marek.belisko@gmail.com>2013-05-03 07:37:36 +0200
committerMark Brown <broonie@opensource.wolfsonmicro.com>2013-05-03 09:29:59 +0100
commitdf4a4eece78b484ea3c29aa1f9e9a03fcbb56c8b (patch)
tree11b826a2a9a474249fc13abe351fc05889fb1072 /sound
parent81ee6833bc6ccd0c64d2f527775a3ded7aa9bfb4 (diff)
ASoC: McASP: Fix receive clock polarity in DAIFMT_NB_NF mode.
According documentation bit ACLKRPOL is set to 0 (receiver samples data on falling edge) and when set to 1 (receiver samples data on rising edge). I2S data are always sampled on falling edge and valid during rising edge of bit clock. So in case of capture data transmitter sample data on falling edge and macsp must read then on rising edge. Signed-off-by: Marek Belisko <marek.belisko@streamunlimited.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'sound')
-rw-r--r--sound/soc/davinci/davinci-mcasp.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/sound/soc/davinci/davinci-mcasp.c b/sound/soc/davinci/davinci-mcasp.c
index 9acb72c5f65..660d00e7f6f 100644
--- a/sound/soc/davinci/davinci-mcasp.c
+++ b/sound/soc/davinci/davinci-mcasp.c
@@ -566,7 +566,7 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
mcasp_clr_bits(base + DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
- mcasp_clr_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
+ mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
mcasp_clr_bits(base + DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
break;