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authorArchit Taneja <archit@ti.com>2013-03-26 19:15:22 +0530
committerTomi Valkeinen <tomi.valkeinen@ti.com>2013-04-10 15:02:52 +0300
commitca5ca69cab83f9efc301ba0b44dc4f71bb167050 (patch)
tree2d867a4aa8029380636ce140a326f6bc9a771744 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/SchedGui.py
parent5303b3aa77a175a6a312aee6867e740ad1809171 (diff)
omapdss: DISPC: add max pixel clock limits for LCD and TV managers
Each version of OMAP has a limitation on the maximum pixel clock frequency supported by an overlay manager. This limit isn't checked by omapdss. Add dispc feats for lcd and tv managers and check whether the target timings can be supported or not. The pixel clock limitations are actually more complex. They depend on which OPP OMAP is in, and they also depend on which encoder is the manager connected to. The OPP dependence is ignored as DSS forces the PM framework to be on OPP100 when DSS is enabled, and the encoder dependencies are ignored by DISPC for now. These limits should come from the encoder driver. The OMAP2 TRM doesn't mention the maximum pixel clock limit. This value is left as half of DSS_FCLK, as OMAP2 requires the PCD to be atleast 2. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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