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authorPaulo Zanoni <paulo.r.zanoni@intel.com>2013-11-25 15:27:08 -0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-12-12 15:30:47 +0100
commit566b734a190766f25f21c8c44633c14a122e61fa (patch)
tree26e2b16fb646bb56abce5d94c05d81555c35441d /virt
parent47e9766df0298739aab87c9874a21feb71560953 (diff)
drm/i915: split intel_ddi_pll_mode_set in 2 pieces
The first piece, intel_ddi_pll_select, finds a PLL and assigns it to the CRTC, but doesn't write any register. It can also fail in case it doesn't find a PLL. The second piece, intel_ddi_pll_enable, uses the information stored by intel_ddi_pll_select to actually enable the PLL by writing to its register. This function can't fail. We also have some refcount sanity checks here. The idea is that one day we'll remove all the functions that touch registers from haswell_crtc_mode_set to haswell_crtc_enable, so we'll call intel_ddi_pll_select at haswell_crtc_mode_set and then call intel_ddi_pll_enable at haswell_crtc_enable. Since I'm already touching this code, let's take care of this particular split today. v2: - Clock on the debug message is in KHz - Add missing POSTING_READ Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> [danvet: Bikeshed comments.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'virt')
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