diff options
| -rw-r--r-- | drivers/video/nvidia/nv_hw.c | 15 | ||||
| -rw-r--r-- | drivers/video/nvidia/nv_setup.c | 3 | ||||
| -rw-r--r-- | drivers/video/riva/nv_driver.c | 6 | ||||
| -rw-r--r-- | drivers/video/riva/riva_hw.c | 12 |
4 files changed, 23 insertions, 13 deletions
diff --git a/drivers/video/nvidia/nv_hw.c b/drivers/video/nvidia/nv_hw.c index ea426115c6f..f297c7b14a4 100644 --- a/drivers/video/nvidia/nv_hw.c +++ b/drivers/video/nvidia/nv_hw.c @@ -686,7 +686,7 @@ static void nForceUpdateArbitrationSettings(unsigned VClk, if ((par->Chipset & 0x0FF0) == 0x01A0) { unsigned int uMClkPostDiv; - dev = pci_find_slot(0, 3); + dev = pci_get_bus_and_slot(0, 3); pci_read_config_dword(dev, 0x6C, &uMClkPostDiv); uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf; @@ -694,11 +694,11 @@ static void nForceUpdateArbitrationSettings(unsigned VClk, uMClkPostDiv = 4; MClk = 400000 / uMClkPostDiv; } else { - dev = pci_find_slot(0, 5); + dev = pci_get_bus_and_slot(0, 5); pci_read_config_dword(dev, 0x4c, &MClk); MClk /= 1000; } - + pci_dev_put(dev); pll = NV_RD32(par->PRAMDAC0, 0x0500); M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; @@ -707,19 +707,21 @@ static void nForceUpdateArbitrationSettings(unsigned VClk, sim_data.pix_bpp = (char)pixelDepth; sim_data.enable_video = 0; sim_data.enable_mp = 0; - pci_find_slot(0, 1); + dev = pci_get_bus_and_slot(0, 1); pci_read_config_dword(dev, 0x7C, &sim_data.memory_type); + pci_dev_put(dev); sim_data.memory_type = (sim_data.memory_type >> 12) & 1; sim_data.memory_width = 64; - dev = pci_find_slot(0, 3); + dev = pci_get_bus_and_slot(0, 3); pci_read_config_dword(dev, 0, &memctrl); + pci_dev_put(dev); memctrl >>= 16; if ((memctrl == 0x1A9) || (memctrl == 0x1AB) || (memctrl == 0x1ED)) { int dimm[3]; - pci_find_slot(0, 2); + dev = pci_get_bus_and_slot(0, 2); pci_read_config_dword(dev, 0x40, &dimm[0]); dimm[0] = (dimm[0] >> 8) & 0x4f; pci_read_config_dword(dev, 0x44, &dimm[1]); @@ -731,6 +733,7 @@ static void nForceUpdateArbitrationSettings(unsigned VClk, printk("nvidiafb: your nForce DIMMs are not arranged " "in optimal banks!\n"); } + pci_dev_put(dev); } sim_data.mem_latency = 3; diff --git a/drivers/video/nvidia/nv_setup.c b/drivers/video/nvidia/nv_setup.c index 336ddb0d10b..707e2c8a13e 100644 --- a/drivers/video/nvidia/nv_setup.c +++ b/drivers/video/nvidia/nv_setup.c @@ -261,7 +261,7 @@ static void nv10GetConfig(struct nvidia_par *par) } #endif - dev = pci_find_slot(0, 1); + dev = pci_get_bus_and_slot(0, 1); if ((par->Chipset & 0xffff) == 0x01a0) { int amt = 0; @@ -276,6 +276,7 @@ static void nv10GetConfig(struct nvidia_par *par) par->RamAmountKBytes = (NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10; } + pci_dev_put(dev); par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ? 14318 : 13500; diff --git a/drivers/video/riva/nv_driver.c b/drivers/video/riva/nv_driver.c index be630a0ccfd..a11026812d1 100644 --- a/drivers/video/riva/nv_driver.c +++ b/drivers/video/riva/nv_driver.c @@ -231,12 +231,14 @@ unsigned long riva_get_memlen(struct riva_par *par) case NV_ARCH_30: if(chipset == NV_CHIP_IGEFORCE2) { - dev = pci_find_slot(0, 1); + dev = pci_get_bus_and_slot(0, 1); pci_read_config_dword(dev, 0x7C, &amt); + pci_dev_put(dev); memlen = (((amt >> 6) & 31) + 1) * 1024; } else if (chipset == NV_CHIP_0x01F0) { - dev = pci_find_slot(0, 1); + dev = pci_get_bus_and_slot(0, 1); pci_read_config_dword(dev, 0x84, &amt); + pci_dev_put(dev); memlen = (((amt >> 4) & 127) + 1) * 1024; } else { switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & diff --git a/drivers/video/riva/riva_hw.c b/drivers/video/riva/riva_hw.c index e0b8c521cc9..70bfd78eca8 100644 --- a/drivers/video/riva/riva_hw.c +++ b/drivers/video/riva/riva_hw.c @@ -1118,8 +1118,9 @@ static void nForceUpdateArbitrationSettings unsigned int uMClkPostDiv; struct pci_dev *dev; - dev = pci_find_slot(0, 3); + dev = pci_get_bus_and_slot(0, 3); pci_read_config_dword(dev, 0x6C, &uMClkPostDiv); + pci_dev_put(dev); uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf; if(!uMClkPostDiv) uMClkPostDiv = 4; @@ -1132,8 +1133,9 @@ static void nForceUpdateArbitrationSettings sim_data.enable_video = 0; sim_data.enable_mp = 0; - dev = pci_find_slot(0, 1); + dev = pci_get_bus_and_slot(0, 1); pci_read_config_dword(dev, 0x7C, &sim_data.memory_type); + pci_dev_put(dev); sim_data.memory_type = (sim_data.memory_type >> 12) & 1; sim_data.memory_width = 64; @@ -2112,12 +2114,14 @@ static void nv10GetConfig * Fill in chip configuration. */ if(chipset == NV_CHIP_IGEFORCE2) { - dev = pci_find_slot(0, 1); + dev = pci_get_bus_and_slot(0, 1); pci_read_config_dword(dev, 0x7C, &amt); + pci_dev_put(dev); chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024; } else if(chipset == NV_CHIP_0x01F0) { - dev = pci_find_slot(0, 1); + dev = pci_get_bus_and_slot(0, 1); pci_read_config_dword(dev, 0x84, &amt); + pci_dev_put(dev); chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024; } else { switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF) |