diff options
| -rw-r--r-- | arch/mips/lib/iomap.c | 2 | ||||
| -rw-r--r-- | include/asm-mips/io.h | 18 |
2 files changed, 19 insertions, 1 deletions
diff --git a/arch/mips/lib/iomap.c b/arch/mips/lib/iomap.c index 7e2ced715cf..f4ac5bbcd81 100644 --- a/arch/mips/lib/iomap.c +++ b/arch/mips/lib/iomap.c @@ -63,7 +63,7 @@ void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) return ioport_map(start, len); if (flags & IORESOURCE_MEM) { if (flags & IORESOURCE_CACHEABLE) - return ioremap_cacheable_cow(start, len); + return ioremap_cachable(start, len); return ioremap_nocache(start, len); } diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 5a4c8a54b8f..8c011aa61af 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -283,6 +283,24 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, __ioremap_mode((offset), (size), _CACHE_UNCACHED) /* + * ioremap_cachable - map bus memory into CPU space + * @offset: bus address of the memory + * @size: size of the resource to map + * + * ioremap_nocache performs a platform specific sequence of operations to + * make bus memory CPU accessible via the readb/readw/readl/writeb/ + * writew/writel functions and the other mmio helpers. The returned + * address is not guaranteed to be usable directly as a virtual + * address. + * + * This version of ioremap ensures that the memory is marked cachable by + * the CPU. Also enables full write-combining. Useful for some + * memory-like regions on I/O busses. + */ +#define ioremap_cachable(offset, size) \ + __ioremap_mode((offset), (size), PAGE_CACHABLE_DEFAULT) + +/* * These two are MIPS specific ioremap variant. ioremap_cacheable_cow * requests a cachable mapping, ioremap_uncached_accelerated requests a * mapping using the uncached accelerated mode which isn't supported on |